Overview
In this tutorial we will create a peripheral containing the Aurora core to implement a high speed serial transceiver with a RocketIO MGT. It will be an improved version of the Aurora transceiver developed in the tutorial titled Create an Aurora Transceiver. The improvement is achieved by connecting the peripheral to the PLB rather than the OPB, which allows much faster data transfer by virtue of a wider bus and Direct Memory Access capability.

To test the design, we will instantiate two Aurora peripherals, assign them to different RocketIO MGTs and place a SATA cable between them to create a loop-back connection. The PowerPC will transfer data between the two Aurora peripherals simply by reading and writing to the read and write FIFOs. To test the design, the test application will write data to the write FIFO of the first Aurora peripheral and read it back from the read FIFO of the second Aurora peripheral. To take advantage of the full PLB bandwidth, the PowerPC will read and write to the FIFOs using DMA transfers. The Aurora peripheral will also have outputs indicating the status of the link. These outputs will be connected to the LEDs on the XUPV2P board.

Figure: The Aurora peripheral

The diagram above illustrates the design of the Aurora peripheral. It uses a read and write FIFO to transfer data between the PowerPC and the user logic. It also uses a second pair of FIFOs called the RX and TX FIFOs. The RX and TX FIFOs create a buffered link between the read/write FIFOs and the Aurora core. This buffered link is necessary because the PLB clock and the RocketIO clock are independent on the XUPV2P board. The PLB clocks data in and out of the read/write FIFOs at 100MHz while the user logic clocks data in and out of the Aurora core at 75MHz. For this reason, we use RX and TX FIFOs with independent read and write clock inputs.

The TX and RX FIFOs are connected to the Aurora core through a multiplexer and demultiplexer respectively. The FIFOs have a width of 64 bits to utilize the complete PLB data width. We will generate an Aurora core with a 16 bit wide interface because the MGTs are optimized for a width of 2 words, that is 16 bits if we are using 8B/10B encoding. The MUX and DEMUX are needed to connect the 64 bit FIFO interface to the 16 bit Aurora core interface. The MUX converts each 64 bit entry from the TX FIFO into groups of 16 bits spread over 4 clock cycles. The DEMUX buffers 4 x 16 bit words from the Aurora core into one 64 bit entry to the RX FIFO. This configuration allows us to make full use of the PLB bandwidth.

As in the MGT Oscillator project, we will also create a Digital Clock Manager (DCM) peripheral for the RocketIO MGTs. The DCM peripheral will only contain two clock buffers and will not require registers or FIFOs.

This tutorial starts the user from scratch, assuming that the Aurora core license has been installed, and contains screenshots to guide the user through the entire implementation process. You can click on the images to view a higher resolution when necessary.

Requirements
Apart from the obvious requirements (XPS software and XUPV2P board) this project requires the following:

1. SATA cable: If you are using the XUPV2P board, a SATA cable is necessary to be able to verify this design. If you do not have a SATA cable, you can buy one from most computer/electronics stores or from Digikey (part number 3M5568-ND). If you are not using the XUPV2P board, you must have a way to physically connect two MGTs.
2. CORE Generator: Both the Aurora core and the TX/RX FIFOs will be created with the CORE Generator. Before beginning this tutorial, you will need to register with Xilinx to obtain a license to use the Aurora core. It is a free and simple process that involves accepting the license agreement after which you are emailed a license with instructions on unlocking the Aurora core in your CORE Generator. To start your registration, follow this link:http://www.xilinx.com/aurora/register_aurora.htm

Create the Basic Project
Follow these steps to create the basic project:

1. Open XPS and from the dialog box, select “Base System Builder wizard” and OK.
2. Create a new folder for the project and select it using “Browse”. In “Advanced Options” tick “Use repository paths” and select the “C:\XUPV2P\lib” folder using “Browse”. Click “OK”.
3. Tick “I would like to create a new design” and click “Next”.
4. Select “Xilinx” as the board vendor. Select “XUP Virtex II Pro Development System” as the board name. Select “C” as the board revision. Click “Next”.
5. Tick “PowerPC” and click “Next”.
6. Select all clock frequencies to be 100MHz. Select “No debug”. Click “Next”.
7. In selecting the Additional IO Interfaces, tick “onewire_0″ and “RS232_Uart_1″. Untick everything else. We will not actually use the “onewire_0″ interface in this project, but leaving it in has shown to be important. For an explanation, refer to “The Onewire Problem” on the Known Issues page.
8. When Adding Internal Peripherals, select 64KB for the “plb_bram_if_cntlr_1″ and click “Next”.
9. Select “RS232_Uart_1″ for both STDIN and STDOUT. Un-tick “Memory Test” and leave “Peripheral Test” ticked. Click “Next”.
10. On the “Configure Peripheral Test Application” page, select “plb_bram_if_cntlr_1″ for the Instruction, Data, Stack and Heap memories. Click “Next”.
11. Click “Generate”.
12. Click “Finish”.
13. Tick “Start using Platform Studio” and click “OK”.

Create the DCM Peripheral
Follow these steps to create the DCM peripheral:

1. Select from the menu “Hardware->Create or Import Peripheral”. Click “Next”.
2. Select “Create templates for a new peripheral” and click “Next”.
3. Select “To an XPS project” and click “Next”.
4. Type “mgt_dcm” for the peripheral name. Click “Next”.
5. Select “On-chip Peripheral Bus” (OPB) and click “Next”.
6. The DCM peripheral is very simple and doesn’t need interrupts, registers or FIFOs. Un-tick everything and click “Next”.
7. On the “IP Interconnect” page, leave everything as is. Click “Next”.
8. On the “Peripheral Simulation Support” page, click “Next” without ticking the option to generate.
9. After the “Peripheral Implementation Support” page, the wizard will generate all the template files for us. Tick “Generate ISE and XST project files” and “Generate template driver files”. Click “Next”.
10. Click “Finish”. Now our templates are created.

Modify the DCM Peripheral
Now we will add code in our peripheral template to instantiate two clock buffers that will generate the clock sources REF_CLK and USER_CLK for the RocketIO MGTs. This DCM example originates from the Xilinx RocketIO Transceiver User Guide (ug024), see section “Digital Clock Manager (DCM) Examples”.

1. Select from the menu “File->Open” and from the project folder, browse to “pcores\mgt_dcm_v1_00_a\hdl\vhdl”.
2. Open the file “mgt_dcm.vhd”.
3. Find the line of code that says “– ADD USER PORTS BELOW THIS LINE” and add the following lines of code just below.

  TOP_BREF_CLK_P : in std_logic;
  TOP_BREF_CLK_N : in std_logic;
  TOP_BREF_CLK   : out std_logic;
  USER_CLK       : out std_logic;

1. Find the line of code that says “– MAP USER PORTS BELOW THIS LINE” and add the following lines of code just below.

  TOP_BREF_CLK_P => TOP_BREF_CLK_P,
  TOP_BREF_CLK_N => TOP_BREF_CLK_N,
  TOP_BREF_CLK => TOP_BREF_CLK,
  USER_CLK => USER_CLK,

1. Save and close the file.
2. Select from the menu “File->Open” and from the project folder, browse to “pcores\mgt_dcm_v1_00_a\hdl\vhdl”.
3. Open the file “user_logic.vhd”.
4. Find the line of code that says “– ADD USER PORTS BELOW THIS LINE” and add the following lines of code just below.

  TOP_BREF_CLK_P : in std_logic;
  TOP_BREF_CLK_N : in std_logic;
  TOP_BREF_CLK   : out std_logic;
  USER_CLK       : out std_logic;

1. Find the line of code that says “–USER signal declarations added here” and add the following lines of code just below.

component IBUFGDS_LVDS_25
  port(
    O  : out std_ulogic;
    I  : in  std_ulogic;
    IB : in  std_ulogic
  );
end component;

component BUFG
  port(
    O : out std_ulogic;
    I : in  std_ulogic
  );
end component;

signal top_bref_clk_i : std_logic;
signal user_clk_i  : std_logic;

1. Find the line of code that says “–USER logic implementation added here” and add the following lines of code just below.

-- Differential Clock Buffer for top BREF_CLK
diff_clk_buff_top_i : IBUFGDS_LVDS_25
  port map(
    I  => TOP_BREF_CLK_P,
    IB => TOP_BREF_CLK_N,
    O  => top_bref_clk_i
  );

-- BUFG used to drive USER_CLK on global clock net
user_clock_bufg_i : BUFG
  port map(
    I => top_bref_clk_i,
    O => user_clk_i
  );

TOP_BREF_CLK <= top_bref_clk_i;
USER_CLK <= user_clk_i;

1. Save and close the file.

Import the DCM Peripheral
Now we will use the Peripheral Wizard to import the DCM peripheral.

1. Select from the menu “Hardware->Create or Import Peripheral” and click “Next”.
2. Select “Import existing peripheral” and click “Next”.
3. Select “To an XPS project”, ensure that the folder chosen is the project folder, and click “Next”.
4. For the name of the peripheral, type “mgt_dcm”. Tick “Use version” and select the same version number that we originally created. Click “Next”. It will ask if we are willing to overwrite the existing peripheral and we should answer “Yes”.
5. Tick “HDL source files” and click “Next”.
6. Select “Use existing Peripheral Analysis Order file (*.pao)” and click “Browse”. From the project folder, go to “pcores\mgt_dcm_v1_00_a\data” and select the “mgt_dcm_v2_1_0.pao” file. Click “Next”.
7. On the HDL analysis information page, click “Next”. The wizard will mention if any errors are found in the design.
8. On the Bus Interfaces page, tick “OPB Slave” and click “Next”.
9. On the SOPB: Port page, click “Next”.
10. On the SOPB: Parameter page, click “Next”.
11. On the “Identify Interrupt Signals” page, un-tick “Select and configure interrupt(s)” and click “Next”.
12. On the “Parameter Attributes” page, click “Next”.
13. On the “Port Attributes” page, click “Next”.
14. Click “Finish”.

The DCM peripheral should now be accessible through the “IP Catalog->Project Repository” in the XPS interface.

Create an Instance of the DCM Peripheral
Follow these steps to create an instance of the peripheral in the project.

1. From the “IP Catalog” find the “mgt_dcm” IP core in the “Project Repository” group. Right click on the core and select “Add IP”.
2. From the “System Assembly View” using the “Bus Interface” filter, connect the “mgt_dcm_0″ to the OPB bus.
3. Click on the “Ports” filter. Click on the “+” for “mgt_dcm_0″ to view its ports.
4. Click on the “Net” field for the “TOP_BREF_CLK_P” port. Type “TOP_BREF_CLK_P” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
5. Click on the “Net” field for the “TOP_BREF_CLK_N” port. Type “TOP_BREF_CLK_N” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
6. Click on the “Net” field for the “TOP_BREF_CLK” port. Type “TOP_BREF_CLK” in this field and press “Enter”.
7. Click on the “Net” field for the “USER_CLK” port. Type “USER_CLK” in this field and press “Enter”. The result should look like the image below.
8. Now if you click the “+” for “External Ports”, you should be able to find the two ports “TOP_BREF_CLK_P_pin” and “TOP_BREF_CLK_N_pin”, with nets called “TOP_BREF_CLK_P” and “TOP_BREF_CLK_N” respectively.
9. Click on the “Addresses” filter. Change the “Size” for “mgt_dcm_0″ to 64K. Then click “Generate Addresses”.

Now we have an instance of the DCM peripheral in the project. The single DCM peripheral will supply the reference clock to all the MGTs accessible on the XUPV2P board.

Create the Aurora Peripheral
Now we will start the creation of the Aurora peripheral by using the Peripheral Wizard. The Wizard will create a template for us with the read and write FIFOs fully implemented. We will then modify the template to include the Aurora core and RX/TX FIFOs. Follow these steps to create the Aurora peripheral.

1. Select from the menu “Hardware->Create or Import Peripheral”. Click “Next”.
2. Select “Create templates for a new peripheral” and click “Next”.
3. Select “To an XPS project” and click “Next”.
4. Type “aurora_plb” for the peripheral name. Click “Next”.
5. Select “Processor Local Bus” (PLB) and click “Next”.
6. On the “IPIF Services” page, tick “Burst transaction support”, “FIFO” and “DMA”. Un-tick everything else and click “Next”.
7. For the FIFO Service settings, leave the defaults ticked: Include read FIFO, Include write FIFO, Use packet mode, Use vacancy calculation. Choose 64-bits for the width of the FIFOs, and choose a depth of 512.
8. On the “IP Interconnect” page leave everything as is. Click “Next”.
9. On the “Peripheral Simulation Support” page, click “Next” without ticking the option to generate.
10. After the “Peripheral Implementation Support” page, tick “Generate ISE and XST project files” and “Generate template driver files”. Click “Next”.
11. Click “Finish”. Now our templates are created.

Now the template is created, we now need to use CORE Generator to create our RX/TX FIFOs and the Aurora core.

Create the FIFO Component in CORE Generator
The read and write FIFOs of our Aurora peripheral were created by the Peripheral Wizard and they are ready for us to use in the user_logic.vhd file. The TX and RX FIFOs however must be created by us and placed into the user_logic.vhd file manually. Fortunately, the CORE Generator provides a good FIFO component that suits our needs. Follow these steps to create the FIFO component that we will use to implement the TX and RX FIFOs.

1. Run the Xilinx CORE Generator. Note that you do not have to close the XPS software.
2. Select “File->New Project”.
3. Click “Browse” and select an appropriate location for a Coregen project. Within a Coregen project, you can create several cores that don’t necessarily relate to each other. Just select the folder where you normally place your projects, and leave the project name as “coregen”. Click “OK”.
4. CORE Generator will ask you if you want to create the “coregen” folder. Click “OK”.
5. You will be asked for the specifications of the FPGA you are using. Under the “Part” tab, select these options: Family “Virtex2P”, Device “xc2vp30″, Package “ff896″, Speed grade “-7″. Click “OK”.
6. When you have created your Coregen project, click on the “View by Function” tab to get a list of cores that you are able to generate.
7. Open “Memories and Storage Elements->FIFOs” and double-click on “FIFO Generator 3.2″.
8. A dialog box should open to allow you to select the features of the FIFO you want. On the first page we select the read and write clock setting. We want asynchronous clocks so we must select “Independent Clocks” using memory type “Block RAM”. Click “Next”.
9. On the second page, we want to select “Standard FIFO” with a “Write width” of 64, a “Write depth” of 512 and a “Read width” of 64. Click “Next”.
10. On the third page, tick “Almost Full Flag”, “Valid Flag” and “Reset Pin”. Click “Finish”. Pages 4, 5 and 6 do not contain any features that we desire.
11. Now use Windows Explorer to browse the “coregen” folder just created. You will find the generated files. One of those files is a netlist file called “fifo_generator_v3_2_fifo_generator_v3_2_xst_1.ngc”. Rename the file to “fifo_generator_v3_2.ngc”. This is the file that we will use in our Aurora peripheral to implement the TX and RX FIFOs.

You can leave the CORE Generator open, because in the next section we will use it again to generate the Aurora core. The FIFO will now be listed under the tab “Generated IP”.

Create the Aurora core in CORE Generator
Once you have a license to use the Aurora core and you have gone through the instructions provided by Xilinx, you should be able to use the CORE Generator to produce an Aurora core. The CORE Generator can generate VHDL code for the Aurora core with many variations as you will see in the creation wizard. Follow these steps to create an Aurora core:

1. Run the Xilinx CORE Generator if it is not already open.
2. We will create the Aurora core in the Coregen project that we created for the FIFO component. If you have not left the Coregen project open from the previous section, click “File->Open Project” and browse to the “coregen” project folder that we just created for the FIFO. Select the “coregen.cgp” file and click “Open”.
3. From the “View by Function” tab, open “Communication and Networking->Serial Interfaces” and double-click on the “Aurora” IP. If you have not registered for a license to use the Aurora core, you will be given a message saying that you do not have permission to generate the core. If you have registered, received and installed the license, you may be given this message: “License for component allows you to use this component, but does not give you access to source code implementing this component”. You can ignore this message as the CORE Generator will in fact give you source code. A dialog box will open that you will use to select the features of the Aurora core.
4. Specify the number of “Aurora Lanes” to be 1, “Bytes per Lane” to be 2, and “Interface” to Streaming. Leave “Special Features” un-ticked. Click “Next”.
5. On the second page we select the reference clock and the MGT we wish to use. The specific MGT to use is not so important because we will be able to change this in our .ucf file later. The row of the clock however is important because the XUPV2P board is wired to use the TOP row. Ignore the comment saying Row 0 is the bottom and Row 1 is the top. For “Row 0 Clock” select “BREF_CLK”. For “Row 1 Clock” select “none”. To select the MGT, put a “1″ in Row 0, Column 0, and place an “X” in all the other squares. Click “Finish”.
6. The Aurora core will be generated and you will see it listed in the “Generated IP” tab.
7. Close CORE Generator.

Exploring the Generated Files
Now if you explore the contents of the “coregen” project folder that CORE Generator created, you should find the files as shown below: The FIFO files of importance to us are the netlist (.ngc) file and the “fifo_generator_v3_2.vho” file. The latter file gives us an example of the FIFO component declaration and instantiation. We will use these examples in the “user_logic.vhd” of our Aurora peripheral code later.

In the “aurora_201″ folder you will find useful documentation and examples for using the Aurora core. The user guide for the Aurora core is the file called “ug061.pdf” and it is recommended that you read this file to better understand the work in this tutorial. Another interesting document is the Getting Started Guide in the file “aurora_gs_ug173.pdf”. This guide explains the example that was generated by the CORE Generator and how to simulate and implement it. In the “aurora_201\examples” folder, you will find the “aurora_sample.vhd” file which is the top-level of the example design. It is important to understand the example because in this tutorial, we will use the example code in our Aurora peripheral “user_logic.vhd” file.

Copy the Aurora core source files
We need to copy the Aurora core source files into the Aurora peripheral source folder. We just generated the source files for the Aurora core with CORE Generator and they should be found in the “coregen” project folder. The image below shows two explorer windows browsing the source code files.

1. Open Windows Explorer and browse to the folder “coregen\aurora_201\src”. Copy all the files in that folder and paste them into the “pcores\aurora_plb_v1_00_a\hdl\vhdl” folder within your XPS project. You will be copying these files into the same folder as your “user_logic.vhd” file for the Aurora peripheral is contained.
2. Now browse to the folder “coregen\aurora_201\cc_manager”. Copy the file “standard_cc_module.vhd” in that folder and paste it into the “pcores\aurora_plb_v1_00_a\hdl\vhdl” folder within your XPS project.
3. Make sure that you have copied all the files listed below.

aurora_201.vhd
aurora_lane.vhd
aurora_pkg.vhd
channel_error_detect.vhd
channel_init_sm.vhd
chbond_count_dec.vhd
error_detect.vhd
global_logic.vhd
idle_and_ver_gen.vhd
lane_init_sm.vhd
phase_align.vhd
rx_stream.vhd
sym_dec.vhd
sym_gen.vhd
tx_stream.vhd
standard_cc_module.vhd

Modify the .PAO file
The .pao file contains a list of all the source files that compose our peripheral. We use this list when we run the Peripheral Wizard in Import mode. Now that we have added the Aurora core source files to the project, we must include them in the .pao file. Note that files must be listed in the .pao file in hierarchical order. The components at the top of the hierarchy are listed at the bottom of the file.

1. Select “File->Open” and browse to the “pcores\aurora_plb_v1_00_a\data” folder. Select the file “aurora_plb_v2_1_0.pao” and click “Open”.
2. At the bottom of this file you will see these two lines:

lib aurora_plb_v1_00_a user_logic vhdl
lib aurora_plb_v1_00_a aurora_plb vhdl

1. Add the following lines just above those two lines. It is important to copy the lines exactly as shown and in the same order.

lib aurora_plb_v1_00_a aurora_pkg vhdl
lib aurora_plb_v1_00_a channel_error_detect vhdl
lib aurora_plb_v1_00_a idle_and_ver_gen vhdl
lib aurora_plb_v1_00_a channel_init_sm vhdl
lib aurora_plb_v1_00_a error_detect vhdl
lib aurora_plb_v1_00_a sym_dec vhdl
lib aurora_plb_v1_00_a sym_gen vhdl
lib aurora_plb_v1_00_a chbond_count_dec vhdl
lib aurora_plb_v1_00_a lane_init_sm vhdl
lib aurora_plb_v1_00_a rx_stream vhdl
lib aurora_plb_v1_00_a tx_stream vhdl
lib aurora_plb_v1_00_a global_logic vhdl
lib aurora_plb_v1_00_a phase_align vhdl
lib aurora_plb_v1_00_a aurora_lane vhdl
lib aurora_plb_v1_00_a standard_cc_module vhdl
lib aurora_plb_v1_00_a aurora_201 vhdl

1. Save the file.

Now we can use this .pao file with the Peripheral Wizard when we import the Aurora peripheral.

Modify the Aurora Peripheral
Now we will add code to our peripheral template to instantiate an Aurora core and the TX and RX FIFOs. The TX and RX FIFOs will be wired to the write and read FIFOs such that data is automatically passed along when any of the FIFOs receives data. We will also include two state machines for multiplexing and demultiplexing the data between the TX/RX FIFOs and the Aurora core.

1. Select from the menu “File->Open” and from the project folder, browse to “pcores\aurora_plb_v1_00_a\hdl\vhdl”.
2. Open the file “aurora_plb.vhd”.
3. Find the line of code that says “– ADD USER PORTS BELOW THIS LINE” and add the following lines of code just below.

  TOP_BREF_CLK      : in std_logic;
  USER_CLK          : in std_logic;
  HARD_ERROR        : out std_logic;
  SOFT_ERROR        : out std_logic;
  LANE_UP           : out std_logic;
  CHANNEL_UP        : out std_logic;
  RXP               : in std_logic;
  RXN               : in std_logic;
  TXP               : out std_logic;
  TXN               : out std_logic;

1. Find the line of code that says “– MAP USER PORTS BELOW THIS LINE” and add the following lines of code just below.

  TOP_BREF_CLK => TOP_BREF_CLK,
  USER_CLK => USER_CLK,
  HARD_ERROR => HARD_ERROR,
  SOFT_ERROR => SOFT_ERROR,
  LANE_UP => LANE_UP,
  CHANNEL_UP => CHANNEL_UP,
  RXP => RXP,
  RXN => RXN,
  TXP => TXP,
  TXN => TXN,

1. Save and close the file.
2. Select from the menu “File->Open” and browse from the project folder to “pcores\aurora_plb_v1_00_a\hdl\vhdl”.
3. Open the file “user_logic.vhd”. We will need to modify this source code to instantiate the Aurora core and TX/RX FIFOs.
4. Find the line of code that says “– ADD USER PORTS BELOW THIS LINE” and add the following lines of code just below.

  TOP_BREF_CLK      : in std_logic;
  USER_CLK          : in std_logic;
  HARD_ERROR        : out std_logic;
  SOFT_ERROR        : out std_logic;
  LANE_UP           : out std_logic;
  CHANNEL_UP        : out std_logic;
  RXP               : in std_logic;
  RXN               : in std_logic;
  TXP               : out std_logic;
  TXN               : out std_logic;

1. Find the line of code that says “–USER signal declarations added here” and add the following lines of code just below. You will recognize this code from the “aurora_sample.vhd” file.

  -- External Register Declarations --
  signal HARD_ERROR_Buffer  : std_logic;
  signal SOFT_ERROR_Buffer  : std_logic;
  signal LANE_UP_Buffer     : std_logic;
  signal CHANNEL_UP_Buffer  : std_logic;
  signal TXP_Buffer         : std_logic;
  signal TXN_Buffer         : std_logic;

  -- Wire Declarations --
  -- Stream TX Interface
  signal tx_d_i         : std_logic_vector(0 to 15);
  signal tx_src_rdy_n_i : std_logic;
  signal tx_dst_rdy_n_i : std_logic;

  -- Stream RX Interface
  signal rx_d_i         : std_logic_vector(0 to 15);
  signal rx_src_rdy_n_i : std_logic;

  -- Error Detection Interface
  signal hard_error_i   : std_logic;
  signal soft_error_i   : std_logic;

  -- Status
  signal channel_up_i   : std_logic;
  signal lane_up_i      : std_logic;

  -- Clock Compensation Control Interface
  signal warn_cc_i      : std_logic;
  signal do_cc_i        : std_logic;

  --TX & RX FIFO signals
  signal tx_fifo_empty : std_logic;
  signal rx_fifo_empty : std_logic;
  signal tx_fifo_we    : std_logic := '0';
  signal rx_fifo_we    : std_logic := '0';
  signal tx_fifo_re    : std_logic := '0';
  signal rx_fifo_re    : std_logic := '0';
  signal tx_fifo_valid : std_logic;
  signal rx_fifo_valid : std_logic;
  signal tx_fifo_almost_full : std_logic;
  signal rx_fifo_almost_full : std_logic;
  signal tx_fifo_dout  : std_logic_vector(63 downto 0);
  signal rx_fifo_dout  : std_logic_vector(63 downto 0);
  signal tx_fifo_din   : std_logic_vector(63 downto 0);
  signal rx_fifo_din   : std_logic_vector(63 downto 0);

  -- State type for MUX and DEMUX state machines
  type STATE_TYPE is (
    IDLE,WAITDATA,WORD0,WORD1,WORD2,WORD3);

  -- MUX state machine signals
  signal mux_c_state        : STATE_TYPE;
  signal mux_n_state        : STATE_TYPE;
  signal mux_din            : std_logic_vector(63 downto 0);
  signal mux_din_buf        : std_logic_vector(63 downto 0);
  signal mux_din_buf_cmb    : std_logic_vector(63 downto 0);
  signal mux_we             : std_logic;
  signal mux_wrreq          : std_logic;
  signal mux_dout           : std_logic_vector(15 downto 0);
  signal mux_dout_cmb       : std_logic_vector(15 downto 0);
  signal mux_dout_valid     : std_logic;
  signal mux_dout_valid_cmb : std_logic;
  signal mux_rdreq          : std_logic;
  signal mux_rdreq_cmb      : std_logic;

  -- DEMUX state machine signals
  signal demux_c_state   : STATE_TYPE;
  signal demux_n_state   : STATE_TYPE;
  signal demux_we        : std_logic;
  signal demux_din       : std_logic_vector(15 downto 0);
  signal demux_dout      : std_logic_vector(63 downto 0);
  signal demux_dout_cmb  : std_logic_vector(63 downto 0);
  signal demux_valid     : std_logic;
  signal demux_valid_cmb : std_logic;

  -- Component Declarations --

  component aurora_201
    generic (
      EXTEND_WATCHDOGS   : boolean := FALSE
    );
    port (
      -- LocalLink TX Interface
        TX_D           : in std_logic_vector(0 to 15);
        TX_SRC_RDY_N   : in std_logic;
        TX_DST_RDY_N   : out std_logic;
      -- LocalLink RX Interface
        RX_D           : out std_logic_vector(0 to 15);
        RX_SRC_RDY_N   : out std_logic;
      -- MGT Serial I/O
        RXP            : in std_logic;
        RXN            : in std_logic;
        TXP            : out std_logic;
        TXN            : out std_logic;
      -- MGT Reference Clock Interface
        TOP_BREF_CLK   : in std_logic;
      -- Error Detection Interface
        HARD_ERROR     : out std_logic;
        SOFT_ERROR     : out std_logic;
      -- Status
        CHANNEL_UP     : out std_logic;
        LANE_UP        : out std_logic;
      -- Clock Compensation Control Interface
        WARN_CC        : in std_logic;
        DO_CC          : in std_logic;
      -- System Interface
        DCM_NOT_LOCKED : in std_logic;
        USER_CLK       : in std_logic;
        RESET          : in std_logic;
        POWER_DOWN     : in std_logic;
        LOOPBACK       : in std_logic_vector(1 downto 0)
      );
  end component;

  component STANDARD_CC_MODULE
    port (
      -- Clock Compensation Control Interface
        WARN_CC        : out std_logic;
        DO_CC          : out std_logic;
      -- System Interface
        DCM_NOT_LOCKED : in std_logic;
        USER_CLK       : in std_logic;
        CHANNEL_UP     : in std_logic
      );
  end component;

  -- FIFO component from CORE Generator
  component fifo_generator_v3_2
    port (
      din         : IN std_logic_VECTOR(63 downto 0);
      rd_clk      : IN std_logic;
      rd_en       : IN std_logic;
      rst         : IN std_logic;
      wr_clk      : IN std_logic;
      wr_en       : IN std_logic;
      almost_full : OUT std_logic;
      dout        : OUT std_logic_VECTOR(63 downto 0);
      empty       : OUT std_logic;
      full        : OUT std_logic;
      valid       : OUT std_logic
    );
  end component;

1. Find the line of code that says “–USER logic implementation added here” and add the following lines of code just below.

  HARD_ERROR  <= HARD_ERROR_Buffer;
  SOFT_ERROR  <= SOFT_ERROR_Buffer;
  LANE_UP     <= LANE_UP_Buffer;
  CHANNEL_UP  <= CHANNEL_UP_Buffer;
  TXP         <= TXP_Buffer;
  TXN         <= TXN_Buffer;

  -- Register User I/O --
  -- Register User Outputs from core.
  process (USER_CLK)
  begin
    if (USER_CLK 'event and USER_CLK = '1') then
      HARD_ERROR_Buffer  <= hard_error_i;
      SOFT_ERROR_Buffer  <= soft_error_i;
      LANE_UP_Buffer     <= lane_up_i;
      CHANNEL_UP_Buffer  <= channel_up_i;
    end if;
  end process;

  -- Aurora core instantiation
  aurora_module_i : aurora_201
    port map (
      -- LocalLink TX Interface
        TX_D           => tx_d_i,
        TX_SRC_RDY_N   => tx_src_rdy_n_i,
        TX_DST_RDY_N   => tx_dst_rdy_n_i,
      -- LocalLink RX Interface
        RX_D           => rx_d_i,
        RX_SRC_RDY_N   => rx_src_rdy_n_i,
      -- MGT Serial I/O
        RXP            => RXP,
        RXN            => RXN,
        TXP            => TXP_Buffer,
        TXN            => TXN_Buffer,
      -- MGT Reference Clock Interface
        TOP_BREF_CLK   => TOP_BREF_CLK,
      -- Error Detection Interface
        HARD_ERROR     => hard_error_i,
        SOFT_ERROR     => soft_error_i,
      -- Status
        CHANNEL_UP     => channel_up_i,
        LANE_UP        => lane_up_i,
      -- Clock Compensation Control Interface
        WARN_CC        => warn_cc_i,
        DO_CC          => do_cc_i,
      -- System Interface
        DCM_NOT_LOCKED => '0',
        USER_CLK       => USER_CLK,
        RESET          => Bus2IP_Reset,
        POWER_DOWN     => '0',
        LOOPBACK       => "00"
      );

  standard_cc_module_i : STANDARD_CC_MODULE
    port map (
      -- Clock Compensation Control Interface
        WARN_CC        => warn_cc_i,
        DO_CC          => do_cc_i,
      -- System Interface
        DCM_NOT_LOCKED => '0',
        USER_CLK       => USER_CLK,
        CHANNEL_UP     => channel_up_i
      );

  -----------------------------------------
  -- FIFOs:
  --  Write FIFO -> TX FIFO -> Aurora TX
  --  Read FIFO <- RX FIFO <- Aurora RX
  --
  -- Write FIFO: Single CLK: Bus2IP_Clk
  -- Read FIFO:  Single CLK: Bus2IP_Clk
  -- TX FIFO:    In CLK: Bus2IP_Clk, Out CLK: USER_CLK
  -- RX FIFO:    In CLK: USER_CLK, Out CLK: Bus2IP_Clk
  --
  tx_fifo_i : fifo_generator_v3_2
    port map (
      din => tx_fifo_din,
      rd_clk => USER_CLK,
      rd_en => tx_fifo_re,
      rst => Bus2IP_Reset,
      wr_clk => Bus2IP_Clk,
      wr_en => tx_fifo_we,
      almost_full => tx_fifo_almost_full,
      dout => tx_fifo_dout,
      empty => tx_fifo_empty,
      full => open,
      valid => tx_fifo_valid);

  rx_fifo_i : fifo_generator_v3_2
    port map (
      din => rx_fifo_din,
      rd_clk => Bus2IP_Clk,
      rd_en => rx_fifo_re,
      rst => Bus2IP_Reset,
      wr_clk => USER_CLK,
      wr_en => rx_fifo_we,
      almost_full => rx_fifo_almost_full,
      dout => rx_fifo_dout,
      empty => rx_fifo_empty,
      full => open,
      valid => rx_fifo_valid);

  ----------------------------------------------------
  -- MUX state machine
  MUX_SM_COMB : process (mux_wrreq, mux_we, mux_c_state) is
  begin
    -- set defaults
    mux_rdreq_cmb <= '0';
    mux_din_buf_cmb <= mux_din_buf;
    mux_dout_cmb <= (others => '0');
    mux_dout_valid_cmb <= '0';
    mux_n_state <= mux_c_state;

    case mux_c_state is
      -- Idle state - waiting for data in tx_fifo
      when IDLE =>
        if mux_wrreq = '1' then
          mux_rdreq_cmb <= '1';
          mux_n_state <= WAITDATA;
        end if;
      -- WAITDATA state - wait a clock cycle
      when WAITDATA =>
        mux_n_state <= WORD0;
      -- WORD0 state - transfer the first word
      when WORD0 =>
        if mux_we = '1' then
          mux_din_buf_cmb <= mux_din;
          mux_dout_cmb <= mux_din(63 downto 48);
          mux_dout_valid_cmb <= '1';
          mux_n_state <= WORD1;
        else
          mux_n_state <= IDLE;
        end if;
      -- WORD1 state - transfer the second word
      when WORD1 =>
        mux_dout_cmb <= mux_din_buf(47 downto 32);
        mux_dout_valid_cmb <= '1';
        mux_n_state <= WORD2;
      -- WORD2 state - transfer the third word
      when WORD2 =>
        mux_dout_cmb <= mux_din_buf(31 downto 16);
        mux_dout_valid_cmb <= '1';
        if mux_wrreq = '1' then
          mux_rdreq_cmb <= '1';
        end if;
        mux_n_state <= WORD3;
      -- WORD3 state - transfer the fourth word
      when WORD3 =>
        mux_dout_cmb <= mux_din_buf(15 downto 0);
        mux_dout_valid_cmb <= '1';
        if mux_rdreq = '1' then
          mux_n_state <= WORD0;
        else
          mux_n_state <= IDLE;
        end if;
      when others =>
        mux_n_state <= IDLE;
    end case;
  end process MUX_SM_COMB;

  -- MUX state controller
  MUX_SM_SEQ : process (USER_CLK) is
  begin
    if USER_CLK'event and USER_CLK = '1' then
      if Bus2IP_Reset = '1' then
        mux_rdreq <= '0';
        mux_din_buf <= (others => '0');
        mux_dout <= (others => '0');
        mux_dout_valid <= '0';
        mux_c_state <= IDLE;
      else
        mux_rdreq <= mux_rdreq_cmb;
        mux_din_buf <= mux_din_buf_cmb;
        mux_dout <= mux_dout_cmb;
        mux_dout_valid <= mux_dout_valid_cmb;
        mux_c_state <= mux_n_state;
      end if;
    end if;
  end process MUX_SM_SEQ;

  ----------------------------------------------------
  -- DEMUX state machine
  DEMUX_SM_COMB : process (demux_we, demux_c_state) is
  begin
    -- set defaults
    demux_valid_cmb <= '0';
    demux_dout_cmb <= demux_dout;
    demux_n_state <= demux_c_state;

    case demux_c_state is
      -- Idle state - waiting for data in tx_fifo
      when IDLE =>
        if demux_we = '1' then
      demux_dout_cmb(63 downto 48) <= demux_din;
          demux_n_state <= WORD1;
        end if;
      -- WORD1 state - copy the second word
      when WORD1 =>
        if demux_we = '1' then
      demux_dout_cmb(47 downto 32) <= demux_din;
          demux_n_state <= WORD2;
        else
      demux_dout_cmb(47 downto 0) <= (others => '0');
          demux_valid_cmb <= '1';
          demux_n_state <= IDLE;
        end if;
      -- WORD2 state - copy the third word
      when WORD2 =>
        if demux_we = '1' then
      demux_dout_cmb(31 downto 16) <= demux_din;
          demux_n_state <= WORD3;
        else
      demux_dout_cmb(31 downto 0) <= (others => '0');
          demux_valid_cmb <= '1';
          demux_n_state <= IDLE;
        end if;
      -- WORD3 state - copy the fourth word
      when WORD3 =>
        if demux_we = '1' then
      demux_dout_cmb(15 downto 0) <= demux_din;
        else
      demux_dout_cmb(15 downto 0) <= (others => '0');
        end if;
        demux_valid_cmb <= '1';
        demux_n_state <= IDLE;
      when others =>
        demux_n_state <= IDLE;
    end case;
  end process DEMUX_SM_COMB;

  -- DEMUX state controller
  DEMUX_SM_SEQ : process (USER_CLK) is
  begin
    if USER_CLK'event and USER_CLK = '1' then
      if Bus2IP_Reset = '1' then
        demux_valid <= '0';
        demux_dout <= (others => '0');
        demux_c_state <= IDLE;
      else
        demux_valid <= demux_valid_cmb;
        demux_dout <= demux_dout_cmb;
        demux_c_state <= demux_n_state;
      end if;
    end if;
  end process DEMUX_SM_SEQ;

  ----------------------------------------------------
  -- Connections between modules

  -- Connection between Write FIFO and TX FIFO
  tx_fifo_we <= WFIFO2IP_RdAck;
  tx_fifo_din <= WFIFO2IP_Data;
  IP2WFIFO_RdReq <= (not WFIFO2IP_empty) and (not tx_fifo_almost_full);

  -- Connection between Read FIFO and RX FIFO
  IP2RFIFO_WrReq <= rx_fifo_valid;
  IP2RFIFO_Data <= rx_fifo_dout;
  rx_fifo_re <= (not rx_fifo_empty) and (not RFIFO2IP_AlmostFull);

  -- Connection between TX FIFO and MUX
  tx_fifo_re <= mux_rdreq;
  mux_din <= tx_fifo_dout;
  mux_we <= tx_fifo_valid;
  mux_wrreq <= not tx_fifo_empty;

  -- Connection between RX FIFO and DEMUX
  rx_fifo_we <= demux_valid;
  rx_fifo_din <= demux_dout;

  -- Connection between MUX and Aurora TX
  tx_src_rdy_n_i <= not mux_dout_valid;
  tx_d_i <= mux_dout;

  -- Connection between DEMUX and Aurora RX
  -- (the Aurora RX has no read request signal)
  demux_we <= not rx_src_rdy_n_i;
  demux_din <= rx_d_i;

1. Now we must remove the example code for the read and write FIFOs. The “user_logic.vhd” file is always generated with code that connects the read and write FIFOs in loop-back. It is intended to provide an example of usage of the FIFOs and also allows for easy testing of a new peripheral. In our design, we have connected the read and write FIFOs to the RX and TX FIFOs respectively, so we must remove the example code. Comment out, or delete all the lines of code from the line that reads “FIFO_CNTL_SM_COMB : process(…” to the line that reads “IP2RFIFO_Data <= WFIFO2IP_Data;” inclusively.
2. Save and close the file.

The MUX and DEMUX state machines that we placed into the “user_logic.vhd” file could be better organized by creating separate components and .vhd files for them. It is only for simplicity of this tutorial that they are placed directly in the “user_logic.vhd” file.

Import the Aurora Peripheral
Now we will use the Peripheral Wizard in Import mode.

1. Select from the menu “Hardware->Create or Import Peripheral” and click “Next”.
2. Select “Import existing peripheral” and click “Next”.
3. Select “To an XPS project”, ensure that the folder chosen is the project folder, and click “Next”.
4. For the name of the peripheral, type “aurora_plb”. Tick “Use version” and select the same version number that we originally created. Click “Next”. It will ask if we are willing to overwrite the existing peripheral and we should answer “Yes”.
5. Tick “HDL source files” and “Netlist files”. We need to click Netlist files because the FIFO component that we use for the TX and RX FIFO is contained in a .ngc file. Click “Next”.
6. Select “Use existing Peripheral Analysis Order file (*.pao)” and click “Browse”. From the project folder, go to “pcores\aurora_plb_v1_00_a\data” and select the “aurora_plb_v2_1_0.pao” file. Click “Next”.
7. On the HDL analysis information page, click “Next”. The wizard will mention if any errors are found in the design.
8. On the Bus Interfaces page, tick “PLB Master and Slave” and click “Next”.
9. On the MSPLB: Port page, click “Next”.
10. On the MSPLB: Parameter page, click “Next”.
11. On the “Identify Interrupt Signals” page, leave the default settings and click “Next”.
12. On the “Parameter Attributes” page, click “Next”.
13. On the “Port Attributes” page, click “Next”.
14. On the “Netlist Files” page, we must specify the location of the .ngc file for the FIFO that we generated earlier with CORE Generator. Click “Select Files” and browse to the “coregen” project folder. Select the file “fifo_generator_v3_2.ngc” and click “Open”. The .ngc file should be listed as shown in the image below. Click “Next”.
15. Click “Finish”.

The peripheral wizard will make a copy of the .ngc file we specified and place it in the “pcores\aurora_plb_v1_00_a\netlist” in our project folder. It will also create a file called “aurora_plb_v2_1_0.bbd” in “pcores\aurora_plb_v1_00_a\data” which is a text file that lists the .ngc files used by the peripheral. The Aurora peripheral should now be accessible through the “IP Catalog->Project Repository” in the XPS interface.

Create two Instances of the Aurora Peripheral
We will create two instances of the Aurora peripheral in this project so that we can connect them with a loop-back SATA cable and transfer data between them. Follow these steps to create two instances of the peripheral in the project.

1. From the “IP Catalog” find the “aurora_plb” IP core in the “Project Repository” group. Right click on the core and select “Add IP”. Do this a second time to add another Aurora peripheral.
2. From the “System Assembly View” using the “Bus Interface” filter, connect the “aurora_plb_0″ and “aurora_plb_1″ to the PLB.
3. Click on the “Ports” filter. Click on the “+” for “aurora_plb_0″ and “aurora_plb_1″ to view their ports.
4. Click on the “Net” field for the “TOP_BREF_CLK” port. Type “TOP_BREF_CLK” in this field and press “Enter”. Do this for both “aurora_plb_0″ and “aurora_plb_1″.
5. Click on the “Net” field for the “USER_CLK” port. Type “USER_CLK” in this field and press “Enter”. Do this for both “aurora_plb_0″ and “aurora_plb_1″.
6. For “aurora_plb_0″ ONLY, click on the “Net” field for the “HARD_ERROR” port. Type “HARD_ERROR” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
7. For “aurora_plb_0″ ONLY, click on the “Net” field for the “SOFT_ERROR” port. Type “SOFT_ERROR” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
8. For “aurora_plb_0″ ONLY, click on the “Net” field for the “LANE_UP” port. Type “LANE_UP” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”. The ports should now look as shown in the image below.
9. For “aurora_plb_0″ ONLY, click on the “Net” field for the “CHANNEL_UP” port. Type “CHANNEL_UP” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”. The ports for both peripherals should be as shown in the screenshot below.
10. Click on the “Addresses” filter. Change the “Size” for “aurora_plb_0″ and “aurora_plb_1″ to 64K. Then click “Generate Addresses”.

Now we have two instances of the Aurora peripheral in the project. Both Aurora peripherals have status outputs (CHANNEL_UP, HARD_ERROR, SOFT_ERROR and LANE_UP) which we would like to connect to the LEDs. We only externalized those ports for the “aurora_plb_0″ peripheral because we only have 4 LEDs to use on the XUPV2P board. As we are going to connect the Aurora peripherals to each other with a loop-back SATA cable, the status outputs of both peripherals should be the same anyway.

Modify the UCF Constraints File
Now we must add some lines to the project’s .ucf file to tell XPS: (1) which physical RocketIO MGT to use, (2) where the external reference clock pins are, (3) the frequency or period of the reference clock, and (4) where the external LED pins are to connect our status outputs.

1. Click on the “Project” tab and double-click on “UCF File: data/system.ucf” from within the “Project Files” tree. The .ucf file should open.
2. Insert the following code at the end of the .ucf file.

##### Timing Contraints for the MGT Recovered clock ######

NET aurora_plb_0/aurora_plb_0/USER_LOGIC_I/aurora_module_i/lane_0_mgt_i/RXRECCLK PERIOD=75 MHz;
NET aurora_plb_1/aurora_plb_1/USER_LOGIC_I/aurora_module_i/lane_0_mgt_i/RXRECCLK PERIOD=75 MHz;

##### Timing Contraints for the MGT reference clock ######

NET USER_CLK PERIOD = 75 MHz;
NET TOP_BREF_CLK PERIOD = 75 MHz;

###### Connect the external MGT clock inputs #######

NET TOP_BREF_CLK_P_pin LOC=F16;
NET TOP_BREF_CLK_P_pin IOSTANDARD = LVDS_25;
NET TOP_BREF_CLK_N_pin LOC=G16;
NET TOP_BREF_CLK_N_pin IOSTANDARD = LVDS_25;

###### MGT Locations #######

# X0Y1 (SATA 0 HOST) aurora_plb_0
INST aurora_plb_0/aurora_plb_0/USER_LOGIC_I/aurora_module_i/lane_0_mgt_i LOC=GT_X0Y1;
# X1Y1 (SATA 1 TARGET) aurora_plb_1
INST aurora_plb_1/aurora_plb_1/USER_LOGIC_I/aurora_module_i/lane_0_mgt_i LOC=GT_X1Y1;

###### Connect LEDs to the Aurora Status outputs ########

# LED 0
NET CHANNEL_UP_pin LOC = AC4;
Net CHANNEL_UP_pin IOSTANDARD = LVTTL;
Net CHANNEL_UP_pin SLEW = SLOW;
Net CHANNEL_UP_pin DRIVE = 12;
# LED 1
NET HARD_ERROR_pin LOC = AC3;
Net HARD_ERROR_pin IOSTANDARD = LVTTL;
Net HARD_ERROR_pin SLEW = SLOW;
Net HARD_ERROR_pin DRIVE = 12;
# LED 2
NET SOFT_ERROR_pin LOC = AA6;
Net SOFT_ERROR_pin IOSTANDARD = LVTTL;
Net SOFT_ERROR_pin SLEW = SLOW;
Net SOFT_ERROR_pin DRIVE = 12;
# LED 3
NET LANE_UP_pin LOC = AA5;
Net LANE_UP_pin IOSTANDARD = LVTTL;
Net LANE_UP_pin SLEW = SLOW;
Net LANE_UP_pin DRIVE = 12;

1. Save and close the file.

Modify the Software Application
Now all we need to do is modify the software application to test our Aurora peripherals.

1. From the “Applications” tab, open “Sources” within the “Project: TestApp_Peripheral” tree. Open the “TestApp_Peripheral.c” source file.
2. Replace all the code in this file with the following source and save the file.

#include "xparameters.h"
#include "xbasic_types.h"
#include "xstatus.h"
#include "aurora_plb.h"

Xuint32 *aurora_plb_0_baseaddr_p =
                  (Xuint32 *) XPAR_AURORA_PLB_0_BASEADDR;
Xuint32 *aurora_plb_1_baseaddr_p =
                  (Xuint32 *) XPAR_AURORA_PLB_1_BASEADDR;
Xuint32 aurora_plb_0_baseaddr;
Xuint32 aurora_plb_1_baseaddr;

int main (void)
{
  Xuint32 i;
  Xuint16 data[20];
  Xuint32 data_byte_len;
  Xuint32 data_word_len;

  // Check that the Aurora peripherals exist
  XASSERT_NONVOID(aurora_plb_0_baseaddr_p != XNULL);
  aurora_plb_0_baseaddr = (Xuint32) aurora_plb_0_baseaddr_p;
  XASSERT_NONVOID(aurora_plb_1_baseaddr_p != XNULL);
  aurora_plb_1_baseaddr = (Xuint32) aurora_plb_1_baseaddr_p;

  // Reset read and write FIFOs to initial state
  AURORA_PLB_mResetWriteFIFO(aurora_plb_0_baseaddr);
  AURORA_PLB_mResetReadFIFO(aurora_plb_0_baseaddr);
  AURORA_PLB_mResetWriteFIFO(aurora_plb_1_baseaddr);
  AURORA_PLB_mResetReadFIFO(aurora_plb_1_baseaddr);

  // set data for transmission
  data[0] = 0x1111;
  data[1] = 0x2222;
  data[2] = 0x3333;
  data[3] = 0x4444;
  data[4] = 0x5555;
  data[5] = 0x6666;
  data[6] = 0x7777;
  data[7] = 0x8888;
  data[8] = 0x9999;
  data[9] = 0xAAAA;
  data_word_len = 10;
  data_byte_len = data_word_len * 2;

  // Clear screen
  xil_printf("%c[2J",27);

  xil_printf("Test 1: Transmit data from ");
  xil_printf("AURORA_PLB_0 to AURORA_PLB_1\n\r");
  xil_printf("---------------------------");
  xil_printf("----------------------------\n\r");

  // Write data to AURORA_PLB_0 write FIFO
  xil_printf("  Writing data to the AURORA_PLB_0 peripheral:");
  xil_printf("\n\r    ");
  // Setup DMA transfer from data buffer to aurora_plb_0
  AURORA_PLB_mResetDMA0(aurora_plb_0_baseaddr);
  AURORA_PLB_mSetDMA0Control(aurora_plb_0_baseaddr,
           DMA_SINC_MASK | DMA_DLOCAL_MASK);
  AURORA_PLB_DMA0Transfer(aurora_plb_0_baseaddr, (Xuint32)data,
           aurora_plb_0_baseaddr+AURORA_PLB_WRFIFO_DATA_OFFSET,
           data_byte_len);
  // Wait for the transfer to finish
  while(AURORA_PLB_mDMA0Done(aurora_plb_0_baseaddr) == 0){
  }
  // Check if there was an error with the transaction
  if(AURORA_PLB_mDMA0Error(aurora_plb_0_baseaddr))
    xil_printf("Error writing to AURORA_PLB_0");
  else{
    // Display the written data
    for(i = 0; i < data_word_len; i++)
      xil_printf("0x%04x ", data[i]);
  }
  // Get data from AURORA_PLB_1 read FIFO
  xil_printf("\n\r\n\r  ");
  xil_printf("Reading data from the AURORA_PLB_1 peripheral:");
  xil_printf("\n\r    ");
  // Setup DMA transfer from aurora_plb_1 to data buffer
  AURORA_PLB_mResetDMA0(aurora_plb_1_baseaddr);
  AURORA_PLB_mSetDMA0Control(aurora_plb_1_baseaddr,
           DMA_DINC_MASK | DMA_SLOCAL_MASK);
  AURORA_PLB_DMA0Transfer(aurora_plb_1_baseaddr,
           aurora_plb_1_baseaddr+AURORA_PLB_RDFIFO_DATA_OFFSET,
           (Xuint32)data, data_byte_len);
  // Wait for the transfer to finish
  while(AURORA_PLB_mDMA0Done(aurora_plb_1_baseaddr) == 0){
  }
  // Check if there was an error with the transaction
  if(AURORA_PLB_mDMA0Error(aurora_plb_1_baseaddr))
    xil_printf("Error reading from AURORA_PLB_1");
  else{
    // Display the read data
    for(i = 0; i < data_word_len; i++)
      xil_printf("0x%04x ", data[i]);
  }

  xil_printf("\n\r\n\rTest 2: Transmit data from ");
  xil_printf("AURORA_PLB_1 to AURORA_PLB_0\n\r");
  xil_printf("----------------------------");
  xil_printf("---------------------------\n\r");

  // Write data to AURORA_PLB_1 write FIFO
  xil_printf("  Writing data to the AURORA_PLB_1 peripheral:");
  xil_printf("\n\r    ");
  // Setup DMA transfer from data buffer to aurora_plb_1
  AURORA_PLB_mResetDMA0(aurora_plb_1_baseaddr);
  AURORA_PLB_mSetDMA0Control(aurora_plb_1_baseaddr,
           DMA_SINC_MASK | DMA_DLOCAL_MASK);
  AURORA_PLB_DMA0Transfer(aurora_plb_1_baseaddr, (Xuint32)data,
           aurora_plb_1_baseaddr+AURORA_PLB_WRFIFO_DATA_OFFSET,
           data_byte_len);
  // Wait for the transfer to finish
  while(AURORA_PLB_mDMA0Done(aurora_plb_1_baseaddr) == 0){
  }
  // Check if there was an error with the transaction
  if(AURORA_PLB_mDMA0Error(aurora_plb_1_baseaddr))
    xil_printf("Error writing to AURORA_PLB_1");
  else{
    // Display the written data
    for(i = 0; i < data_word_len; i++)
      xil_printf("0x%04x ", data[i]);
  }
  // Get data from AURORA_PLB_0 Read FIFO
  xil_printf("\n\r\n\r  ");
  xil_printf("Reading data from the AURORA_PLB_0 peripheral:");
  xil_printf("\n\r    ");
  // Setup DMA transfer from aurora_plb_0 to data buffer
  AURORA_PLB_mResetDMA0(aurora_plb_0_baseaddr);
  AURORA_PLB_mSetDMA0Control(aurora_plb_0_baseaddr,
           DMA_DINC_MASK | DMA_SLOCAL_MASK);
  AURORA_PLB_DMA0Transfer(aurora_plb_0_baseaddr,
           aurora_plb_0_baseaddr+AURORA_PLB_RDFIFO_DATA_OFFSET,
           (Xuint32)data, data_byte_len);
  // Wait for the transfer to finish
  while(AURORA_PLB_mDMA0Done(aurora_plb_0_baseaddr) == 0){
  }
  // Check if there was an error with the transaction
  if(AURORA_PLB_mDMA0Error(aurora_plb_0_baseaddr))
    xil_printf("Error reading from AURORA_PLB_0");
  else{
    // Display the read data
    for(i = 0; i < data_word_len; i++)
      xil_printf("0x%04x ", data[i]);
  }

  xil_printf("\n\r\n\r");

  while(1){
  }
}

1. Save and close the file.

Download and Test the Project

1. Open a Hyperterminal window with the required settings. For the correct settings, see Hyperterminal Settings.
2. Connect a SATA cable between the SATA connectors “SATA 0 HOST” and “SATA 1 TARGET” on the XUPV2P board. Note: Never connect a standard SATA cable between “SATA 0 HOST” and “SATA 2 HOST” because this would short together two MGT transmit outputs. In other words, only connect “HOST” to “TARGET”, never “HOST” to “HOST”.
3. Turn on the XUPV2P board.
4. From the XPS software, select “Device Configuration->Download Bitstream”.

The Hyperterminal output will show the results of two data transfer tests between “aurora_plb_0″ and “aurora_plb_1″. In the first test we transfer arbitrary data from “aurora_plb_0″ to “aurora_plb_1″. In the second test we transfer the same data from “aurora_plb_1″ to “aurora_plb_0″. The Hyperterminal output should look as shown in the image below:

The LEDs should display the status outputs: LED 0 – CHANNEL_UP, LED 1 – HARD_ERROR, LED 2 – SOFT_ERROR and LED 3 – LANE_UP. Note that due to the wiring of the LEDs on the XUPV2P, a logic high (“1″) turns the LED OFF, while a logic low (“0″) turns the LED ON. Try disconnecting the SATA cable and see how the status outputs change. The CHANNEL_UP and LANE_UP LEDs should turn ON. If we re-connect the SATA cable, the channel should be re-established and the CHANNEL_UP and LANE_UP LEDs should turn OFF.

By connecting the Aurora peripheral to the PLB, we eliminated the bottleneck of the OPB that limited the “real” data rate of our previous design in Create an Aurora Transceiver. As a further advantage, by using DMA transfers, the PowerPC is free to do other processing while data is automatically transferred to and from the Aurora peripherals.