Tri-mode Ethernet MAC

On October 20, 2008, in Version 10.1, Xilinx Platform Studio (XPS), by Jeff

Tutorial Overview

The Virtex-5 Embedded Tri-mode Ethernet MAC is useful for designs requiring Ethernet connectivity. Fortunately, Xilinx has made it easy for us to start developing with the Ethernet MACs by providing several online examples and application notes. One of the examples can be obtained when you use CORE Generator to generate the Ethernet MAC wrapper. The generated example is a simple design that mirrors incoming Ethernet packets, swapping the source and destination MAC addresses. In this tutorial, we implement the example design provided by CORE Generator by working the example code into a custom peripheral for EDK 10.1.

This tutorial contains screenshots to guide you through the entire implementation process. Click on the images to view a higher resolution.

Requirements

Before following this tutorial, you will need to do the following:

  • Generate the Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper using CORE Generator. For instructions on doing this, please refer to the tutorial Generating the Ethernet MAC
  • Set the J22 and J23 jumpers on the ML505 to positions 2-3 as shown below. This allows us to use an SGMII (serial) interface with the PHY.
     
  • Install a copy of Wireshark on a PC with a Gigabit Ethernet network card
  • Obtain a CAT5 Ethernet cable: regular or crossover, either will work because the PHY on the ML505 has an automatic switching feature that detects what type of cable you are using and switches the TX and RX pins if necessary.
  • Buy an ML505/ML506/ML507 or XUPV5 board if you don’t already have one. Xilinx supplies the ML50x boards, but the best deal is the XUPV5 from Digilent. Click the Digilent link on this page for more information.

Create the Basic Project

Follow these steps to create the basic project:

  1. Open XPS. From the dialog box, select “Base System Builder wizard” and OK.
  2. You will be asked to specify which folder to place the project. Click “Browse” and create a new folder for the project. Click “OK”.
     
  3. We are given the choice to create a new project or to create one using the template of another project. Tick “I would like to create a new design” and click “Next”.
  4. On the “Select Board” page, select “Xilinx” as the board vendor. Select “Virtex 5 ML505 Evaluation Platform” as the board name. Select “1″ as the board revision. Click “Next”.
     
  5. On the “Select Processor” page, we normally have a choice between using the PowerPC “hard” processor, or the Microblaze “soft” processor. Since the Virtex-5 does not contain any PowerPCs, we can only select Microblaze. Click “Next”.
     
  6. On the “Configure Microblaze” page, select the clock frequency to be 125MHz. For the BRAM local memory, select “64KB”. We will use the RS232 port for debugging rather than the JTAG, so select “No debug”. Click “Next”.
     
  7. In selecting the Additional IO Interfaces, leave “RS232_Uart_1″ ticked and un-tick everything else.



     
  8. On the “Add Internal Peripherals” page, click “Next”.
  9. On the “Software Setup” page, select “RS232_Uart_1″ for both STDIN and STDOUT. Un-tick “Memory Test” and leave “Peripheral Test” ticked. Click “Next”.
     
  10. Click “Generate”.
  11. Click “Finish”.

Create the Ethernet MAC Peripheral

We now create our Ethernet MAC peripheral using the Peripheral Wizard.

  1. Select from the menu “Hardware->Create or Import Peripheral”. Click “Next”.
  2. Select “Create templates for a new peripheral” and click “Next”.
     
  3. We must now decide where to place the files for the peripheral. They can be placed within this project, or they can be made accessible to other projects. Select “To an XPS project”. Click “Next”.
  4. On the “Name and Version” page, type “eth_mac” for the peripheral name. Click “Next”.
     
  5. On the “Bus Interface” page, select “Processor Local Bus” (PLB) and click “Next”.
     
  6. On the “IPIF Services” page, select “Include data phase timer”. Un-tick everything else and click “Next”.
     
  7. On the “Slave Interface” page, leave the defaults and click “Next”.
     
  8. On the “Peripheral Simulation Support” page, we can specify if we want the wizard to create a simulation platform for our peripheral. Click “Next” without ticking the option to generate.
  9. After the “Peripheral Implementation Support” page, the wizard will generate all the template files for us. Tick “Generate ISE and XST project files” and “Generate template driver files”. Click “Next”.
  10. Click “Finish”. Now our templates are created and we can modify them to include the code for the timer.

Copy the Ethernet MAC source files

We need to copy the Ethernet MAC source files generated by CORE Generator into the Ethernet MAC peripheral source folder. If you have not generated the source files using CORE Generator, please refer to the tutorial Generating the Ethernet MAC.

  1. Open Windows Explorer and browse to the folder “TEMACCore\v5_emac_v1_5″. This is the folder you created with CORE Generator.
     
  2. In that folder, you will find a subfolder called “example_design”. Copy the “example_design” folder into the “pcores\eth_mac_v1_00_a\hdl\vhdl” folder within your XPS project. This is the folder where you should find your “user_logic.vhd” file for the Ethernet MAC peripheral.

 

Modify the .PAO file

The .pao file contains a list of all the source files that compose our peripheral. We use this list when we run the Peripheral Wizard in Import mode. Now that we have added the Ethernet MAC example source files to the project, we must include them in the .pao file. Note that files must be listed in the .pao file in hierarchical order. The components at the top of the hierarchy are listed at the bottom of the file.

  1. Select “File->Open” and browse to the “pcores\eth_mac_v1_00_a\data” folder. Select the file “eth_mac_v2_1_0.pao” and click “Open”.
  2. At the bottom of this file you will see these two lines:
lib eth_mac_v1_00_a user_logic vhdl
lib eth_mac_v1_00_a eth_mac vhdl
  1. Add the following lines just above those two lines. It is important to copy the lines exactly as shown and in the same order.
lib eth_mac_v1_00_a example_design/v5_emac_v1_5.vhd
lib eth_mac_v1_00_a example_design/physical/rx_elastic_buffer.vhd
lib eth_mac_v1_00_a example_design/physical/gtp_dual_1000X.vhd
lib eth_mac_v1_00_a example_design/physical/rocketio_wrapper_gtp.vhd
lib eth_mac_v1_00_a example_design/physical/rocketio_wrapper_gtp_tile.vhd
lib eth_mac_v1_00_a example_design/v5_emac_v1_5_block.vhd
lib eth_mac_v1_00_a example_design/client/fifo/tx_client_fifo_8.vhd
lib eth_mac_v1_00_a example_design/client/fifo/rx_client_fifo_8.vhd
lib eth_mac_v1_00_a example_design/client/fifo/eth_fifo_8.vhd
lib eth_mac_v1_00_a example_design/v5_emac_v1_5_locallink.vhd
lib eth_mac_v1_00_a example_design/client/address_swap_module_8.vhd
  1. Save the file.

Now we can use this .pao file with the Peripheral Wizard when we import the Ethernet MAC peripheral.

Modify the Ethernet MAC Peripheral

If you refer back to the example design source files created by CORE Generator, you will find the top module contained in the file “v5_emac_v1_5\example_design\v5_emac_v1_5_example_design.vhd”. We copied that file into our peripheral source folder, but we wont directly use it in our design (notice that we didn’t include it in our .pao file). Instead, we will take the code from this file and work it into our “user_logic.vhd” file, the top module for our peripheral.

  1. Select from the menu “File->Open” and look in the project folder.
  2. Open the folders: “pcores\eth_mac_v1_00_a\hdl\vhdl”.
  3. Open the file “eth_mac.vhd”.
  4. Find the line of code that says “– ADD USER PORTS BELOW THIS LINE” and add the following lines of code just below.
  REFCLK_N_IN              : in std_logic;
  REFCLK_P_IN              : in std_logic;
  GTP_READY                : out std_logic;
  PHY_RESET_0              : out std_logic;
  RXP_IN                   : in std_logic;
  RXN_IN                   : in std_logic;
  TXP_OUT                  : out std_logic;
  TXN_OUT                  : out std_logic;
  1. Find the line of code that says “– MAP USER PORTS BELOW THIS LINE” and add the following lines of code just below.
  REFCLK_N_IN  => REFCLK_N_IN,
  REFCLK_P_IN  => REFCLK_P_IN,
  GTP_READY    => GTP_READY,
  PHY_RESET_0  => PHY_RESET_0,
  RXP_IN       => RXP_IN,
  RXN_IN       => RXN_IN,
  TXP_OUT      => TXP_OUT,
  TXN_OUT      => TXN_OUT,
  1. Save and close the file.
  2. Open the file “user_logic.vhd”. We will need to modify this source code to include our example code.
  3. Find the line of code that says “–USER libraries added here” and add the following lines of code just below.
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
  1. Find the line of code that says “– ADD USER PORTS BELOW THIS LINE” and add the following lines of code just below.
  REFCLK_N_IN              : in std_logic;
  REFCLK_P_IN              : in std_logic;
  GTP_READY                : out std_logic;
  PHY_RESET_0              : out std_logic;
  RXP_IN                   : in std_logic;
  RXN_IN                   : in std_logic;
  TXP_OUT                  : out std_logic;
  TXN_OUT                  : out std_logic;
  1. Find the line of code that says “–USER signal declarations added here” and add the following lines of code just below.
  -- Component Declaration for the TEMAC wrapper with
  -- Local Link FIFO.
  component v5_emac_v1_5_locallink is
   port(
      -- EMAC0 Clocking
      -- 125MHz clock output from transceiver
      CLK125_OUT                : out std_logic;
      -- 125MHz clock input from BUFG
      CLK125                    : in  std_logic;
      -- Tri-speed clock output from EMAC0
      CLIENT_CLK_OUT_0          : out std_logic;
      -- EMAC0 Tri-speed clock input from BUFG
      client_clk_0              : in  std_logic;

      -- Local link Receiver Interface - EMAC0
      RX_LL_CLOCK_0             : in  std_logic;
      RX_LL_RESET_0             : in  std_logic;
      RX_LL_DATA_0              : out std_logic_vector(7 downto 0);
      RX_LL_SOF_N_0             : out std_logic;
      RX_LL_EOF_N_0             : out std_logic;
      RX_LL_SRC_RDY_N_0         : out std_logic;
      RX_LL_DST_RDY_N_0         : in  std_logic;
      RX_LL_FIFO_STATUS_0       : out std_logic_vector(3 downto 0);

      -- Local link Transmitter Interface - EMAC0
      TX_LL_CLOCK_0             : in  std_logic;
      TX_LL_RESET_0             : in  std_logic;
      TX_LL_DATA_0              : in  std_logic_vector(7 downto 0);
      TX_LL_SOF_N_0             : in  std_logic;
      TX_LL_EOF_N_0             : in  std_logic;
      TX_LL_SRC_RDY_N_0         : in  std_logic;
      TX_LL_DST_RDY_N_0         : out std_logic;

      -- Client Receiver Interface - EMAC0
      EMAC0CLIENTRXDVLD         : out std_logic;
      EMAC0CLIENTRXFRAMEDROP    : out std_logic;
      EMAC0CLIENTRXSTATS        : out std_logic_vector(6 downto 0);
      EMAC0CLIENTRXSTATSVLD     : out std_logic;
      EMAC0CLIENTRXSTATSBYTEVLD : out std_logic;

      -- Client Transmitter Interface - EMAC0
      CLIENTEMAC0TXIFGDELAY     : in  std_logic_vector(7 downto 0);
      EMAC0CLIENTTXSTATS        : out std_logic;
      EMAC0CLIENTTXSTATSVLD     : out std_logic;
      EMAC0CLIENTTXSTATSBYTEVLD : out std_logic;

      -- MAC Control Interface - EMAC0
      CLIENTEMAC0PAUSEREQ       : in  std_logic;
      CLIENTEMAC0PAUSEVAL       : in  std_logic_vector(15 downto 0);

      --EMAC-MGT link status
      EMAC0CLIENTSYNCACQSTATUS  : out std_logic;
      -- EMAC0 Interrupt
      EMAC0ANINTERRUPT          : out std_logic;

      -- Clock Signals - EMAC0

      -- SGMII Interface - EMAC0
      TXP_0                     : out std_logic;
      TXN_0                     : out std_logic;
      RXP_0                     : in  std_logic;
      RXN_0                     : in  std_logic;
      PHYAD_0                   : in  std_logic_vector(4 downto 0);
      RESETDONE_0               : out std_logic;

      -- unused transceiver
      TXN_1_UNUSED              : out std_logic;
      TXP_1_UNUSED              : out std_logic;
      RXN_1_UNUSED              : in  std_logic;
      RXP_1_UNUSED              : in  std_logic;

      -- SGMII RocketIO Reference Clock buffer inputs
      CLK_DS                    : in  std_logic;

      -- Asynchronous Reset
      RESET                     : in  std_logic
   );
  end component;

   ---------------------------------------------------------------------
   --  Component Declaration for 8-bit address swapping module
   ---------------------------------------------------------------------
   component address_swap_module_8
   port (
      rx_ll_clock         : in  std_logic;
      rx_ll_reset         : in  std_logic;
      rx_ll_data_in       : in  std_logic_vector(7 downto 0);
      rx_ll_sof_in_n      : in  std_logic;
      rx_ll_eof_in_n      : in  std_logic;
      rx_ll_src_rdy_in_n  : in  std_logic;
      rx_ll_data_out      : out std_logic_vector(7 downto 0);
      rx_ll_sof_out_n     : out std_logic;
      rx_ll_eof_out_n     : out std_logic;
      rx_ll_src_rdy_out_n : out std_logic;
      rx_ll_dst_rdy_in_n  : in  std_logic
      );
   end component;

  ------------------------
  -- Signal Declarations
  ------------------------

  -- address swap transmitter connections - EMAC0
  signal tx_ll_data_0_i      : std_logic_vector(7 downto 0);
  signal tx_ll_sof_n_0_i     : std_logic;
  signal tx_ll_eof_n_0_i     : std_logic;
  signal tx_ll_src_rdy_n_0_i : std_logic;
  signal tx_ll_dst_rdy_n_0_i : std_logic;

  -- address swap receiver connections - EMAC0
  signal rx_ll_data_0_i      : std_logic_vector(7 downto 0);
  signal rx_ll_sof_n_0_i     : std_logic;
  signal rx_ll_eof_n_0_i     : std_logic;
  signal rx_ll_src_rdy_n_0_i : std_logic;
  signal rx_ll_dst_rdy_n_0_i : std_logic;

  -- create a synchronous reset in the transmitter clock domain
  signal ll_pre_reset_0_i    : std_logic_vector(5 downto 0);
  signal ll_reset_0_i        : std_logic;

  attribute async_reg : string;
  attribute async_reg of ll_pre_reset_0_i : signal is "true";

  signal resetdone_0_i       : std_logic;

  -- EMAC0 Clocking signals

  -- Transceiver output clock (REFCLKOUT at 125MHz)
  signal user_clk_out              : std_logic;
  -- 125MHz clock input to wrappers
  signal user_clk                  : std_logic;
  -- Input 125MHz differential clock for transceiver
  signal ref_clk                   : std_logic;

  -- 1.25/12.5/125MHz clock signals for tri-speed SGMII
  signal client_clk_0_o            : std_logic;
  signal client_clk_0              : std_logic;
  1. Find the line of code that says “–USER logic implementation added here” and add the following lines of code just below.
  -- PHY Reset logic
  PHY_RESET_0 <= not Bus2IP_Reset;   -- EMAC0 Clocking   -- Generate the clock input to the GTP   -- clk_ds can be shared between multiple MAC instances.   clkingen : IBUFDS port map (     I  => REFCLK_P_IN,
    IB => REFCLK_N_IN,
    O  => ref_clk);

  -- 125MHz from transceiver is routed through a BUFG and
  -- input to the MAC wrappers.
  -- This clock can be shared between multiple MAC instances.
  bufg_clk125 : BUFG port map (I => user_clk_out, O => user_clk);

  -- 1.25/12.5/125MHz clock from the MAC is routed through a BUFG and
  -- input to the MAC wrappers to clock the client interface.
  bufg_client_0 : BUFG port map (I => client_clk_0_o, O => client_clk_0);

  --------------------------------------------
  -- Instantiate the EMAC Wrapper with LL FIFO
  -- (v5_emac_v1_5_locallink.v)
  --------------------------------------------
  v5_emac_ll : v5_emac_v1_5_locallink
  port map (
    -- EMAC0 Clocking
    -- 125MHz clock output from transceiver
    CLK125_OUT                => user_clk_out,
    -- 125MHz clock input from BUFG
    CLK125                    => user_clk,
    -- Tri-speed clock output from EMAC0
    CLIENT_CLK_OUT_0          => client_clk_0_o,
    -- EMAC0 Tri-speed clock input from BUFG
    CLIENT_CLK_0              => client_clk_0,
    -- Local link Receiver Interface - EMAC0
    RX_LL_CLOCK_0             => user_clk,
    RX_LL_RESET_0             => ll_reset_0_i,
    RX_LL_DATA_0              => rx_ll_data_0_i,
    RX_LL_SOF_N_0             => rx_ll_sof_n_0_i,
    RX_LL_EOF_N_0             => rx_ll_eof_n_0_i,
    RX_LL_SRC_RDY_N_0         => rx_ll_src_rdy_n_0_i,
    RX_LL_DST_RDY_N_0         => rx_ll_dst_rdy_n_0_i,
    RX_LL_FIFO_STATUS_0       => open,

    -- Unused Receiver signals - EMAC0
    EMAC0CLIENTRXDVLD         => open,
    EMAC0CLIENTRXFRAMEDROP    => open,
    EMAC0CLIENTRXSTATS        => open,
    EMAC0CLIENTRXSTATSVLD     => open,
    EMAC0CLIENTRXSTATSBYTEVLD => open,

    -- Local link Transmitter Interface - EMAC0
    TX_LL_CLOCK_0             => user_clk,
    TX_LL_RESET_0             => ll_reset_0_i,
    TX_LL_DATA_0              => tx_ll_data_0_i,
    TX_LL_SOF_N_0             => tx_ll_sof_n_0_i,
    TX_LL_EOF_N_0             => tx_ll_eof_n_0_i,
    TX_LL_SRC_RDY_N_0         => tx_ll_src_rdy_n_0_i,
    TX_LL_DST_RDY_N_0         => tx_ll_dst_rdy_n_0_i,

    -- Unused Transmitter signals - EMAC0
    CLIENTEMAC0TXIFGDELAY     => "00000000",
    EMAC0CLIENTTXSTATS        => open,
    EMAC0CLIENTTXSTATSVLD     => open,
    EMAC0CLIENTTXSTATSBYTEVLD => open,

    -- MAC Control Interface - EMAC0
    CLIENTEMAC0PAUSEREQ       => '0',
    CLIENTEMAC0PAUSEVAL       => "0000000000000000",

    --EMAC-MGT link status
    EMAC0CLIENTSYNCACQSTATUS  => GTP_READY,
    -- EMAC0 Interrupt
    EMAC0ANINTERRUPT          => open,

    -- Clock Signals - EMAC0
    -- SGMII Interface - EMAC0
    TXP_0                     => TXP_OUT,
    TXN_0                     => TXN_OUT,
    RXP_0                     => RXP_IN,
    RXN_0                     => RXN_IN,
    PHYAD_0                   => "00010",
    RESETDONE_0               => resetdone_0_i,

    -- unused transceiver
    TXN_1_UNUSED              => open,
    TXP_1_UNUSED              => open,
    RXN_1_UNUSED              => '1',
    RXP_1_UNUSED              => '0',

    -- SGMII RocketIO Reference Clock buffer inputs
    CLK_DS                    => ref_clk,

    -- Asynchronous Reset
    RESET                     => Bus2IP_Reset
  );

  --------------------------------------------
  --  Instatiate the address swapping module
  --------------------------------------------
  client_side_asm_emac0 : address_swap_module_8
    port map (
      rx_ll_clock         => user_clk,
      rx_ll_reset         => ll_reset_0_i,
      rx_ll_data_in       => rx_ll_data_0_i,
      rx_ll_sof_in_n      => rx_ll_sof_n_0_i,
      rx_ll_eof_in_n      => rx_ll_eof_n_0_i,
      rx_ll_src_rdy_in_n  => rx_ll_src_rdy_n_0_i,
      rx_ll_data_out      => tx_ll_data_0_i,
      rx_ll_sof_out_n     => tx_ll_sof_n_0_i,
      rx_ll_eof_out_n     => tx_ll_eof_n_0_i,
      rx_ll_src_rdy_out_n => tx_ll_src_rdy_n_0_i,
      rx_ll_dst_rdy_in_n  => tx_ll_dst_rdy_n_0_i
  );

  rx_ll_dst_rdy_n_0_i     <= tx_ll_dst_rdy_n_0_i;

  -- Create synchronous reset in the transmitter clock domain.
  gen_ll_reset_emac0 : process (user_clk, Bus2IP_Reset)
  begin
    if Bus2IP_Reset = '1' then
      ll_pre_reset_0_i <= (others => '1');
      ll_reset_0_i     <= '1';
    elsif user_clk'event and user_clk = '1' then
      if resetdone_0_i = '1' then
        ll_pre_reset_0_i(0)          <= '0';
        ll_pre_reset_0_i(5 downto 1) <= ll_pre_reset_0_i(4 downto 0);
        ll_reset_0_i                 <= ll_pre_reset_0_i(5);
      end if;
    end if;
  end process gen_ll_reset_emac0;
  1. Save and close the file.

If you examine the “v5_emac_v1_5_example_design.vhd” from the CORE Generator output, you will see that most of the code we inserted into “user_logic.vhd” was directly copied from the example code. The main differences are:

  • PHY Reset: We needed to add a signal (PHY_RESET_0) to drive the external Ethernet PHY reset pin. The PHY on the ML505 board has an active low reset input, so we connect it to the logical “not” of the bus reset signal.
  • The clock signal names were changed for clarity. Most Xilinx documents refer to these clocks as REFCLK and USERCLK.

Import the Ethernet MAC Peripheral

Now we will use the Peripheral Wizard again, but this time using the import function.

  1. Select from the menu “Hardware->Create or Import Peripheral” and click “Next”.
  2. Select “Import existing peripheral” and click “Next”.
     
  3. Select “To an XPS project”, ensure that the folder chosen is the project folder, and click “Next”.
  4. For the name of the peripheral, type “eth_mac”. Tick “Use version” and select the same version number that we originally created. Click “Next”. It will ask if we are willing to overwrite the existing peripheral and we should answer “Yes”.
     
  5. Tick “HDL source files” and click “Next”.
     
  6. Select “Use existing Peripheral Analysis Order file (*.pao)” and click “Browse”. From the project folder, go to “pcores\eth_mac_v1_00_a\data” and select the “eth_mac_v2_1_0.pao” file. Click “Next”.
     
  7. On the “HDL analysis information” page, click “Next”. The wizard will mention if any errors are found in the design.
  8. On the “Bus Interfaces” page, tick “PLB Slave” and click “Next”.
     
  9. On the “SPLB: Port” page, click “Next”.
  10. On the “SPLB: Parameter” page, click “Next”.
  11. On the “Identify Interrupt Signals” page, untick “Select and Configure Interrupts” and click “Next”.
     
  12. On the “Parameter Attributes” page, click “Next”.
  13. On the “Port Attributes” page, click “Next”.
  14. Click “Finish”.

The Ethernet MAC peripheral is now ready to use and it should be accessible through the “IP Catalog->Project Local pcores” in the XPS interface. Note that although we can access it through the IP Catalog, other projects will not find it there because it is only associated with our project, as we specified in the Peripheral Wizard.

Create an Instance of the Peripheral

Now we are ready to create an instance of the peripheral into our project.

  1. From the “IP Catalog” find the “eth_mac” IP core in the “Project Local pcores” group. Right click on the core and select “Add IP”.
     
  2. From the “System Assembly View” using the “Bus Interface” filter, connect the “eth_mac_0″ to the PLB bus.
     
  3. Click on the “Ports” filter. Click on the “+” for “eth_mac_0″ to view its ports.
  4. Click on the “Net” field for the “PHY_RESET_0″ port. Type “PHY_RESET_0″ in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
  5. Click on the “Net” field for the “GTP_READY” port. Type “GTP_READY” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
  6. Click on the “Net” field for the “REFCLK_P_IN” port. Type “REFCLK_P_IN” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
  7. Click on the “Net” field for the “REFCLK_N_IN” port. Type “REFCLK_N_IN” in this field and press “Enter”. Now click again the same field and open the drop down menu. Select “Make External” and press “Enter”.
     
  8. Click on the “Addresses” filter. Change the “Size” for “eth_mac_0″ to 64K. Then click “Generate Addresses”.

Now we have created an instance of the Ethernet MAC peripheral in our design.

Modify the Constraints file

The Ethernet MAC peripheral requires timing and pin constraints, as well as a constraint to select the RocketIO GTP we will use for a link to the PHY. The clocks used must be constrained to 125MHz while the PHY reset and GTP ready signals must be assigned to specific pins. The GTP and pins that we select here were obtained from the schematic for the ML505.

  1. Click the “Project” tab and double click on the UCF file to open it.
  2. Add the following lines to the end of the file:
##################################
# These constraints were adapted from the example
# design produced by CORE Generator:
# v5_emac_v1_5_example_design.ucf
##################################

CONFIG PART = 5vlx50tff1136-1;

##################################
# BLOCK Level constraints
##################################

# EMAC0 Clocking
# 125MHz clock input from BUFG
NET "*user_clk" TNM_NET = "clk_gtp";
TIMEGRP  "v5_emac_v1_5_gtp_clk" = "clk_gtp";
TIMESPEC "TS_v5_emac_v1_5_gtp_clk" = PERIOD "v5_emac_v1_5_gtp_clk" 7700 ps HIGH 50 %;
# EMAC0 Tri-speed clock input from BUFG
NET "*CLIENT_CLK_0" TNM_NET    = "clk_client0";
TIMEGRP  "v5_emac_v1_5_gtp_clk_client0"    = "clk_client0";
TIMESPEC "TS_v5_emac_v1_5_gtp_clk_client0" = PERIOD "v5_emac_v1_5_gtp_clk_client0" 7700 ps HIGH 50 %;

#-----------------------------------------------------------
# EMAC0 Fabric Rx Elastic Buffer Timing Constraints:       -
#-----------------------------------------------------------
NET "*GTP_DUAL_1000X_inst?RXRECCLK_0_BUFR" TNM_NET = "clk_rec_clk0";
TIMEGRP  "v5_emac_v1_5_client_rec_clk0" = "clk_rec_clk0";
TIMESPEC "TS_v5_emac_v1_5_rec_clk0"     = PERIOD "v5_emac_v1_5_client_rec_clk0" 7700 ps HIGH 50 %;

# Control Gray Code delay and skew
INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_addr_gray_?" TNM = "rx_elastic_rd_to_wr_0";
TIMESPEC "TS_rx_elastic_rd_to_wr_0" = FROM "rx_elastic_rd_to_wr_0" TO "clk_rec_clk0" 7500 ps DATAPATHONLY;
INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?wr_addr_gray_?" TNM = "elastic_metastable_0";
TIMESPEC "ts_elastic_meta_protect_0" = FROM "elastic_metastable_0" 5 ns DATAPATHONLY;

# Reduce clock period to allow 3 ns for metastability settling time
INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_wr_addr_gray*" TNM = "rx_graycode_0";
INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_occupancy*"    TNM = "rx_binary_0";
TIMESPEC "ts_rx_buf_meta_protect_0" = FROM "rx_graycode_0" TO "rx_binary_0" 5 ns;

##################################
# LocalLink Level constraints
##################################

# EMAC0 LocalLink client FIFO constraints.

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_tran_frame_tog"    TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_retran_frame_tog"  TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_col_window_pipe_1" TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*"       TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?rd_txfer_tog"         TNM = "tx_fifo_rd_to_wr_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_frame_in_fifo"     TNM = "tx_fifo_wr_to_rd_0";

TIMESPEC "TS_tx_fifo_rd_to_wr_0" = FROM "tx_fifo_rd_to_wr_0" TO "v5_emac_v1_5_gtp_clk_client0" 8000 ps DATAPATHONLY;
TIMESPEC "TS_tx_fifo_wr_to_rd_0" = FROM "tx_fifo_wr_to_rd_0" TO "v5_emac_v1_5_gtp_clk_client0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow 3 ns for metastability settling time
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_tran_frame_tog"    TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*"          TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_txfer_tog"         TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?frame_in_fifo"        TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_tog*" TNM = "tx_metastable_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable_0";

TIMESPEC "ts_tx_meta_protect_0" = FROM "tx_metastable_0" 5 ns DATAPATHONLY;

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*"       TNM = "tx_addr_rd_0";
INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*"          TNM = "tx_addr_wr_0";
TIMESPEC "TS_tx_fifo_addr_0" = FROM "tx_addr_rd_0" TO "tx_addr_wr_0" 10ns;

## RX Client FIFO
# Group the clock crossing signals into timing groups
INST "*client_side_FIFO_emac0?rx_fifo_i?wr_store_frame_tog"   TNM = "rx_fifo_wr_to_rd_0";
INST "*client_side_FIFO_emac0?rx_fifo_i?rd_addr_gray*"        TNM = "rx_fifo_rd_to_wr_0";

TIMESPEC "TS_rx_fifo_wr_to_rd_0" = FROM "rx_fifo_wr_to_rd_0" TO "v5_emac_v1_5_gtp_clk_client0" 8000 ps DATAPATHONLY;
TIMESPEC "TS_rx_fifo_rd_to_wr_0" = FROM "rx_fifo_rd_to_wr_0" TO "v5_emac_v1_5_gtp_clk_client0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow for metastability settling time
INST "*client_side_FIFO_emac0?rx_fifo_i?wr_rd_addr_gray_sync*" TNM = "rx_metastable_0";
INST "*client_side_FIFO_emac0?rx_fifo_i?rd_store_frame_tog"    TNM = "rx_metastable_0";

TIMESPEC "ts_rx_meta_protect_0" = FROM "rx_metastable_0" 5 ns;

##################################
# EXAMPLE DESIGN Level constraints
##################################

# Place the transceiver components. Please alter to your chosen transceiver.
INST "*GTP_DUAL_1000X_inst?GTP_1000X?tile0_rocketio_wrapper_i?gtp_dual_i" LOC = "GTP_DUAL_X0Y3";
NET REFCLK_N_IN_pin  LOC = P3;
NET REFCLK_P_IN_pin  LOC = P4;

##################################
# Additions by FPGA Developer
# http://www.fpgadeveloper.com
##################################

# GTP Ready pin
NET "GTP_READY_pin" LOC = AE24; # LED 7

# PHY Reset pin
NET "PHY_RESET_0_pin" LOC = J14; # ML505 PHY Reset 

# PHY Autonegotiate ON
INST *?v5_emac EMAC0_PHYINITAUTONEG_ENABLE = TRUE;
  1. Save and close the file.

Modify the Software Application

In this example, our software application will not do anything other than send a message to Hyperterminal to let you know that it is running. All processing of Ethernet packets is done in hardware through the Ethernet MAC peripheral.

  1. From the “Applications” tab, open “Sources” within the “Project: TestApp_Peripheral” tree. Open the “TestApp_Peripheral.c” source file.
  2. Replace all the code in this file with the following source and save the file.
#include "xparameters.h"
#include "xbasic_types.h"
#include "xstatus.h"

int main (void)
{
  // Display message
  xil_printf("%c[2J",27);
  xil_printf("Tri-mode Ethernet MAC Loop-back");
  xil_printf(" by FPGA Developer\n\r");
  xil_printf("http://www.fpgadeveloper.com\n\r");

  // Stay in an infinite loop
  while(1){
  }
}

 

Download and Test the Project

  1. Open a Hyperterminal window with the required settings. For the correct settings, see Hyperterminal Settings.
  2. Turn on the ML505 board.
  3. From the XPS software, select “Device Configuration->Download Bitstream”.

The Hyperterminal output should display the message “Tri-mode Ethernet MAC Loop-back by FPGA Developer”. When you get this message, you can continue with the following steps.

  1. Open Wireshark on the PC to be used for testing. You can use any PC with a Gigabit Ethernet network card installed and working.
  2. From the menu select “Edit->Preferences”. In the dialog box that opens, select “User Interface->Columns” and set the columns as shown in the screenshot below. Then click “OK”.
     
  3. From the menu select “Capture->Options”. In the dialog box that opens, select the Gigabit Ethernet network card to which you will connect the ML505, then click “Start”.
     
  4. Connect the CAT5 Ethernet cable between the ML505 and the PC running Wireshark.
  5. You should notice that the Ethernet connection LEDs light up on both the ML505 and the PC. The connection LEDs on the PC should be on the Ethernet (RJ45) connector on the back of your PC. The connection LEDs on the ML505 are located next to the PCI edge connector and they are shown in the photo below.

    In order from left to right, as shown in the photo, the LEDs indicate: CONNECTION, TX, RX, 10Mbps, 100Mbps, 1000Mbps. 
  6. We will produce Ethernet packets from the PC by using “ping”. From Windows, select “Start->Run” and type “cmd”. Press “Enter” and you should have a command prompt. From the command line, type “ping www.google.com”. Note that even before running “ping”, you may already see Ethernet packets in Wireshark. This can happen when your PC is trying to connect to a network.
     
  7. Observe the packets in Wireshark by clicking on them. In the screenshot below, we see that the PC sent packets 1, 3 and 5, while the ML505 sent back packets 2, 4 and 6 with the MAC destination and source addresses swapped. Notice also the short time delay of 225us between the sent packet and the received copy.
     
  8. Also observe that the RX and TX LEDs on the ML505 will light up at the same time, indicating that each packet received is immediately transmitted back to the sender (after swapping the MAC sender/destination addresses).

You can download the project files for this tutorial and try it on your ML50x board. Please select the file corresponding to your board, right-click on it and select “Save Link As”.

Board Virtex-5 Version Project files
ML505 XC5VLX50T EthernetMAC-ML505-EDK10-1.zip
ML506 XC5VSX50T EthernetMAC-ML506-EDK10-1.zip
ML507 XC5VFX70T EthernetMAC-ML507-EDK10-1.zip
XUPV5 XC5VLX110T EthernetMAC-ML509-EDK10-1.zip

 

You now have a working Ethernet connection running at 1Gbps. To develop the project further, remove the address swap module and try some of these ideas:

  • TCP/IP stack: Connect the Ethernet MAC LocalLink interface to read/write FIFOs and run a TCP/IP stack on the Microblaze. A lightweight TCP/IP stack for the Microblaze is discussed in the application note XAPP1026.
  • Ethernet-to-Aurora Bridge: Add an Aurora core to the design and create a transparent bridge.
  • Gigabit PC interface: Don’t bother with TCP/IP and use the Ethernet MAC for a high-speed PC link.
  • Video/audio processing: Use VLC Media Player to stream video into the Virtex-5, then process it and send it out of the DVI interface.

Remember that the interface to the Ethernet MAC is LocalLink, so you can virtually hook up anything with an 8-bit wide LocalLink interface.

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ML505 Tutorials and Examples

On October 19, 2008, in Xilinx Platform Studio (XPS), by Jeff

Here is a maintained list of our step-by-step online tutorials and examples for the Xilinx Virtex-5 FPGA based on the ML505 Evaluation Platform from Xilinx. The following tutorials guide the user through various FPGA designs that combine the Microblaze with custom user logic peripherals.

Xilinx Platform Studio (XPS) Tutorials for ML505

The following tutorials develop working embedded projects that employ the Microblaze soft processor. They are developed using EDK version 10.1 of the Xilinx Platform Studio (XPS).

Version 13.1
  • Convert an ML505 EDK project for the XUPV5

    For some reason, the Base System Builder in EDK doesn't support the XUPV5 board so when making an EDK project for the XUPV5 we have to select the ML505 board and modify the project settings later. If you have not yet created an EDK project, you should ...

  • Creating a project using the Base System Builder

    What am I learning here? In this post we'll look at using the Base System Builder in EDK version 13.1. Specifically you'll learn: How to create an EDK project with the Base System Builder How to add a software application to an EDK project H...

Version 10.1
  • Aurora to Ethernet Bridge

    Tutorial Overview In the last tutorial we implemented the embedded Tri-mode Ethernet MAC and tested it by looping back Ethernet packets and monitoring them with Wireshark. In this tutorial, we will again implement the EMAC but this time we will link...

  • Tri-mode Ethernet MAC

    Tutorial Overview The Virtex-5 Embedded Tri-mode Ethernet MAC is useful for designs requiring Ethernet connectivity. Fortunately, Xilinx has made it easy for us to start developing with the Ethernet MACs by providing several online examples and appl...

  • Other Tutorials and Examples

    Here are links to some useful tutorials and examples hosted on other websites, including Xilinx: Xilinx EDK Concepts, Tools, and Techniques A Hands-on Guide to Effective Embedded System Design

  • Microblaze 16x2 LCD Driver

    Tutorial Overview In this example, we will develop a driver for the 16x2 character LCD on the ML505/6/7 board. The LCD driver will be mostly a Microblaze design, as opposed to being an IP design. The physical interface to the LCD will be made throug...

  • Timer with Interrupts

    Tutorial Overview In this tutorial we will add code to a peripheral template generated by the Peripheral Wizard to create a simple timer. The peripheral will generate an interrupt when the timer expires. The Microblaze will process the interrupt thr...

  • Integrating a VHDL Design into a Peripheral

    Tutorial Overview This tutorial is similar to the previous one titled: Integrating a Blackbox into a Peripheral however in this case, instead of integrating an .ngc file into a peripheral, we integrate one or more VHDL files. Sometimes we have a VHD...

  • Integrating a Blackbox into a Peripheral

    Tutorial Overview Sometimes we have an .ngc file from CORE Generator (or some other source) that we would like to bring into EDK as a peripheral. This project is a simple example of integrating a blackbox design into a peripheral generated by the Pe...

  • Create a Peripheral using the Peripheral Wizard

    Tutorial Overview In this tutorial we will create a simple project that uses our own IP peripheral (instead of using the XPS General Purpose IO peripheral provided by Xilinx) to read from the DIP switches and write to the LEDs. The software applicat...

  • Manually Add a Peripheral to a Project

    Tutorial Overview In the previous example, we created a project using the BSB and all of the work related to the hardware design was done by the BSB. In this example, we will create the same simple project, but this time we will add the GPIO for the...

  • Create a Project Using the Base System Builder

    Tutorial Overview In this example, we will develop a simple FPGA project using the Base System Builder that includes three peripherals: the RS232 UART and two GPIOs. One GPIO will be used for the DIP switches and the other for the LEDs. We will then...

Tutorials and Examples

The examples on this website are provided in a tutorial form. Each tutorial guides the user through the entire process of building a working project from “scratch”. The tutorials guide the user through all steps, with explanations, screen shots and source code. Each tutorial extends or builds on the concepts developed in the previous tutorials. It is recommended that beginners follow the tutorials in sequence.

Scope and Requirements

Most of these projects involve use of the Microblaze soft processor and interfacing it with peripherals developed in VHDL. It is assumed that the reader has a basic understanding of the C programming language and VHDL. All debugging is done through one of the RS232 ports of the ML505 Evaluation Platform. It is therefore necessary that the user have a PC with an RS232 port (comport/serial port) or RS232-to-USB converter, and a copy of Hyperterminal or other terminal program. For the required Hyperterminal settings, click here.

 

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XUPV2P Board

On October 18, 2008, in Xilinx Platform Studio (XPS), by Jeff

Hardware Details

The Xilinx University Program Virtex-II Pro (XUPV2P) Development System from Digilent is a development board for the Virtex-II Pro FPGA. It contains many useful hardware features including:

  • Xilinx Virtex-II Pro XC2VP30 FPGA
  • 10/100Mbps Ethernet PHY
  • USB port
  • Compact Flash card slot
  • XSGA Video port
  • Audio Codec
  • SATA connectors (2 hosts, 1 target)
  • PS/2 and RS-232 ports
  • High and Low Speed expansion connectors

 

Virtex-II Pro FPGA Details

The XUPV2P is loaded with a Virtex-II Pro FPGA:

Board Virtex-II Pro Version Package Speed Grade
XUPV2P XC2VP30 FF896 -7C

For more information, please refer to the Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual.

How to buy it

  1. The XUPV2P can be purchased through the Xilinx University Program from Digilent at only US$299. Click the Digilent link for more information.

 

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Frequently Asked Questions

On October 18, 2008, in General FPGA, by Jeff

FAQs can be a fast way to learn small but important bits of information to help you in your development. Checkout some of our FAQs below:

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ML505/6/7 and XUPV5 FAQ

On October 18, 2008, in Xilinx Platform Studio (XPS), by Jeff

Below are several frequently asked questions about the ML505/6/7 and XUPV5 boards. Click on the question to jump to the answer. If you have a question about the ML505/6/7 or XUPV5 boards, please contact us at the email address given at the end of this page.

 

What is the speed grade of Virtex-5 on my ML505/ML506/ML507/XUPV5 board?

All the ML505/6/7 and XUPV5 boards use a Virtex-5 of speed grade -1.

 

What are the differences between the ML50x boards?

The ML505 has been made in four variations that use the same printed-circuit-board (PCB) but a different version Virtex-5. The table below lists the different boards and the Virtex-5 it is loaded with:

Board Virtex-5 Version Package Speed Grade
ML505 XC5VLX50T FFG1136 -1C
ML506 XC5VSX50T FFG1136 -1C
ML507 XC5VFX70T FFG1136 -1C
XUPV5 XC5VLX110T FFG1136 -1C

For more information, please refer to the ML505/ML506/ML507 Evaluation Platform User Guide.

 

What is the XUPV5 (ML509) board?

The XUPV5 board is a version of the ML505 offered by the Xilinx University Program (XUP). It uses the same printed-circuit-board (PCB) as the ML505 but a Virtex-5 XC5VLX110T rather than the XC5VLX50T. It is also known as the ML509 board because it is labeled so. The board is popular because it can be purchased from Digilent for only US$750.


Why cant I find the XUPV5 (or ML509) board in the Base System Builder (BSB)?

The XUPV5 was only recently released. It should eventually be added to future versions of the EDK. Until then, you can instead select the ML505 board in the BSB and then use “Project->Project Options” to change the Virtex-5 version to the correct one for the XUPV5 board. You may also have to change your constraints file (.ucf) if you use it to specify the FPGA or if you are instantiating RocketIO GTPs. See next question.

 

I have a design for an ML50x board (eg. ML505) that I want to migrate to a different ML50x board (eg. ML509). What do I have to change?

Firstly use “Project->Project Options” to change the Virtex-5 version to the correct one for the board you are migrating to. You may also have to change your constraints file (.ucf) if you use it to specify the FPGA or if you are instantiating RocketIO GTPs. The GTP placement names for one version of Virtex-5 do not necessarily refer to the same GTPs on another Virtex-5. For this reason, you might have to change your .ucf file to specify the correct GTPs that you want to use. Use the table below to ensure that you are using the correct placement names for the board that you are using.

ML505 ML506 ML507 XUPV5
XC5VLX50T XC5VSX50T XC5VFX70T XC5VLX110T
SFP/SMA (BANK116) GTP_DUAL X0Y4 GTP_DUAL X0Y4 GTX_DUAL X0Y5 GTP_DUAL X0Y5
SGMII (BANK112) GTP_DUAL X0Y3 GTP_DUAL X0Y3 GTX_DUAL X0Y4 GTP_DUAL X0Y4
SATA (BANK114) GTP_DUAL X0Y2 GTP_DUAL X0Y2 GTX_DUAL X0Y3 GTP_DUAL X0Y3
PCIe (BANK118) GTP_DUAL X0Y1 GTP_DUAL X0Y1 GTX_DUAL X0Y2 GTP_DUAL X0Y2

 

The banks and their corresponding placement names can be found in the RocketIO User Guides. Refer to “Package Placement Information” in Chapter 4 of the appropriate RocketIO User Guide for your board:

 

The Virtex-5 on my ML50x board gets very hot when in use. What should I do about it?

The Virtex-5 FPGA is a very powerful device that will naturally generate heat when in operation. Several Xilinx application notes suggest using a heatsink/fan with the ML505 board to reduce the overheating problem.

A suitable heatsink/fan can be purchased from Radian Heatsinks. A full list of compatible heatsinks can be found at the link below:

http://www.radianheatsinks.com/docs/virtex-chart.pdf

Other suitable and cost effective heatsinks can be purchased from Digilent. See the list of them in the “Related Products” section of the XUPV5 page.

 

How can I buy an ML50x board and how much does it cost?

  1. The ML505/ML506/ML507 can be purchased from Xilinx for the price of US$1,195.
  2. As an option for universities, the Xilinx University Program offers a version of the board known as the XUPV5 (or ML509). It can be purchased from Digilent for US$750.

 

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ML505/6/7 and XUPV5 Boards

On October 18, 2008, in Xilinx Platform Studio (XPS), by Jeff

Hardware Details

The ML505 Evaluation Platform from Xilinx is a development board for the Virtex-5 FPGA. It contains many useful hardware features including:

  • Xilinx Virtex-5 XC5VLX50T FPGA
  • 10/100/1000 tri-speed Ethernet PHY
  • USB host and peripheral controllers
  • Programmable system clock generator
  • Stereo AC97 codec with line in, line out, headphone, microphone, and SPDIF digital audio jacks
  • PS/2 (2) – Keyboard, Mouse
  • RS-232 port
  • 16×2 character LCD
  • Video Input
  • Video (DVI/VGA) Output
  • DIP Switch (8), LEDs (8), and Pushbuttons (5)
  • PCI Express® Edge Connector (x1 Endpoint)
  • SFP (1000Base-X)

Variations

The ML505 has been made in four variations that use the same printed-circuit-board (PCB) but a different version Virtex-5. The table below lists the different boards and the Virtex-5 it is loaded with:

Board Virtex-5 Version Package Speed Grade
ML505 XC5VLX50T FFG1136 -1C
ML506 XC5VSX50T FFG1136 -1C
ML507 XC5VFX70T FFG1136 -1C
XUPV5 XC5VLX110T FFG1136 -1C

For more information, please refer to the ML505/ML506/ML507 Evaluation Platform User Guide.

How to buy it

  1. The ML505/ML506/ML507 can be purchased from Xilinx for the price of US$1,195.
  2. The best deal for universities, offered by the Xilinx University Program, is a version of the board known as the XUPV5 (or ML509). It can be purchased from Digilent at only US$750. Click the Digilent link for more information.

 

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Generating the Aurora Core

On October 18, 2008, in Core Generator, Version 10.1, by Jeff

Tutorial Overview

In this tutorial, we will generate an Aurora IP core using the Xilinx CORE Generator version 10.1. The Aurora core can be used as a high-speed serial communications link for connecting multiple FPGAs or interfacing to other serial devices.

Requirements

To generate the Aurora core with CORE Generator, you will first need to register with Xilinx to obtain a license to use the Aurora core. It is a free and simple process that involves accepting a license agreement. To start your registration, follow this link:

http://www.xilinx.com/aurora/register_aurora.htm

Once you have successfully registered, you must follow the links to the Aurora downloads and then select “Request LogiCORE IP Aurora License File”. This takes you to the license key request form into which you will enter your email address to receive your license key. The license key will be sent to you by email as an attached .zip file. The email will contain instructions on installing the license key, which basically involves extracting the .zip file contents to your C drive. Once you have extracted the .zip file to your hard drive, you will be able to access the Aurora core in the CORE Generator.

You will also need to do the following:

  • Buy an ML505/ML506/ML507 or XUPV5 board if you don’t already have one. Xilinx supplies the ML50x boards, but the best deal is the XUPV5 from Digilent. Click the Digilent link for more information.

Generate the Aurora IP Core

After installing the license, follow these instructions for generating the Aurora IP core.

  1. From the “Start” menu, open Xilinx CORE Generator.
  2. Select “File->New Project”.
  3. Click “Browse” and select an appropriate location for the Coregen project. Select the folder where you normally place your projects, for example “C:\ML505\Projects”, and create a sub-folder called “AuroraCore”. Open this folder and click “OK”.
  4. You will be asked for the specifications of the FPGA you are using. All the cores you generate under this CORE Generator project file will be customized for the FPGA you specify here. Under the “Part” tab, select these options: Family “Virtex5″, Device “xc5vlx50t”, Package “ff1136″, Speed grade “-1″. Click “OK”. Note: If you are not using the ML505 board, these specifications may not apply to you. You will have to enter the details corresponding to the specific FPGA that you are using.


    Under the “Generation” tab, you can specify how you want your IP cores to be generated. Be sure that “VHDL” output is selected as shown below.

     

  5. When you have created your CORE Generator project, click on the “View by Function” tab to get a list of cores that you are able to generate.
  6. Open “Communication & Networking->Serial Interfaces” and double-click on “Virtex-5 Aurora”.

     

  7. A message box should open saying that you have the “Full license” to use the Aurora core. It may also say that the license does not give you access to the source code, but you can ignore this. Click “OK”.
  8. A dialog box should open to allow you to select the features of the Aurora Core you want. Enter the settings shown in the image below.

     

  9. Click “Finish”. Your Aurora core will be generated and CORE Generator will display a list of all the generated files. Close this window, and close CORE Generator.

Examine the Generated Files

We will now examine the generated files and explain their purpose and utility. Open “Windows Explorer” and browse to the Coregen folder that we just created. We should see a list of files as shown below:

We can see that CORE Generator has placed some files in the coregen project folder, and it has also created a folder specifically for the Aurora core called “aurora_201″. We will discuss the files that you will find most useful.

  • Instantiation Template File (aurora_201.vho)

    The instantiation template provides a template for declaring the Aurora component and instantiating it. If you are already familiar with the Aurora core, you could use this template by copying and pasting it to your design and making the necessary connections. If it is your first time using the Aurora core, you might prefer to use the examples provided in the “aurora_201″ folder.

  • Virtex-5 FPGA Aurora v3.0 User Guide (ug353.pdf)

    The User Guide for the Aurora core provides a detailed description of the workings of the core and the protocol. Read this documentation to better understand how to use and interface to the Aurora core.

     

  • Aurora Core Datasheet (v5_aurora_v3_0.pdf)

    The Aurora core datasheet provides the technical specifications for the Aurora core such as the total resources that it occupies and a short description of its parameters.

     

  • Virtex-5 FPGA Aurora v3.0 Getting Started Guide (v5_aurora_v3_0_gsug352.pdf)

    The getting started guide is probably the most useful document for people new to the Aurora core. It provides an introduction to the Aurora core and gives a detailed description of the example that is generated with the core. It also contains instructions on how to simulate/implement the example.

     

  • Examples folder

    In the “examples” folder you will find the source code for the example described in the Getting Started Guide. The example can be implemented in ISE and it includes a frame generator and frame checker to test the Aurora core in a loopback connection.

     

  • Src folder

    The “src” folder contains the VHDL source for the Aurora core. You will most likely be able to use these files in your designs without having to modify them in any way.

     

  • Testbench folder

    The “testbench” folder contains a testbench for simulating the Aurora core example.

     

  • UCF folder

    The “ucf” folder contains two .ucf constraint files for use with the example design and with the Aurora core. You can use these .ucf files in your designs but you might want to change them to specify a different RocketIO GTP depending on your application.

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Generating the Ethernet MAC

On October 18, 2008, in Core Generator, Version 10.1, by Jeff

Tutorial Overview

The Virtex-5 FPGA is particularly useful in Ethernet applications because it contains embedded Tri-mode 10/100/1000 Mbps Ethernet MACs. If you have done Ethernet designs before, you will know that Xilinx’s “soft” Ethernet MAC IP cores are not free and designing one yourself would be quite an undertaking. In this tutorial, we will generate an embedded Tri-mode Ethernet MAC IP wrapper using the Xilinx CORE Generator version 10.1.

Requirements

Before following this tutorial, you will need to do the following:

  • You will need CORE Generator version 10.1.03 installed for this tutorial.

 

Generate the Tri-mode Ethernet MAC IP Wrapper

Follow these instructions for generating the Ethernet MAC IP wrapper.

  1. From the “Start” menu, open Xilinx CORE Generator.
  2. Select “File->New Project”.
  3. Click “Browse” and select an appropriate location for the Coregen project. Select the folder where you normally place your projects, for example “C:\ML505\Projects”, and create a sub-folder called “TEMACCore”. Open this folder and click “OK”.
  4. You will be asked for the specifications of the FPGA you are using. All the cores you generate under this CORE Generator project file will be customized for the FPGA you specify here. Under the “Part” tab, select these options: Family “Virtex5″, Device “xc5vlx50t”, Package “ff1136″, Speed grade “-1″. Click “OK”. Note: If you are not using the ML505 board, these specifications may not apply to you. You will have to enter the details corresponding to the specific FPGA that you are using.
    Under the “Generation” tab, you can specify how you want your IP cores to be generated. Be sure that “VHDL” output is selected as shown below. 

  5. When you have created your CORE Generator project, click on the “View by Function” tab to get a list of cores that you are able to generate.
  6. Open “Communication & Networking->Ethernet” and double-click on “Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper”.
  7. A dialog box should open to allow you to select the features of the Ethernet MAC Core you want. For each page, enter the settings as shown below.


  8. Click “Finish”. Your Ethernet MAC wrapper will be generated and CORE Generator will display a list of all the generated files. Close this window, and close CORE Generator.

Examine the Generated Files

We will now examine the generated files and explain their purpose and utility. Open “Windows Explorer” and browse to the Coregen folder that we just created. We should see a list of files as shown below:

We can see that CORE Generator has placed some files in the coregen project folder, and it has also created a folder specifically for the Ethernet MAC wrapper called “v5_emac_v1_5″. We will discuss the files that you will find most useful.

  • Instantiation Template File (v5_emac_v1_5.vho)The instantiation template provides a template for declaring the Ethernet MAC component and instantiating it. If you are already familiar with the Ethernet MAC core, you could use this template by copying and pasting it to your design and making the necessary connections. If it is your first time using the core, you might prefer to use the examples provided in the “v5_emac_v1_5″ folder.

  • Ethernet MAC Core Datasheet (doc\v5_emac_ds550.pdf)The datasheet provides the technical specifications for the Ethernet MAC core such as the total resources that it occupies and a short description of its parameters. It also contains an overview of the provided example.
  • Ethernet MAC Core Getting Started Guide (doc\v5_emac_gsg340.pdf)The getting started guide is probably the most useful document for people new to the Ethernet MAC core. It provides an introduction to the core and gives a detailed description of the example that is generated with the core. It also contains instructions on how to simulate/implement the example.
  • Example Design folderIn the “example_design” folder you will find the source code for the example described in the Getting Started Guide and also the wrapper for the Ethernet MAC core. Remember, you will not find VHDL source for the Ethernet MAC, because it is an embedded hardware device, not a “soft” core. In this folder you will also find the .ucf constraints file for use with the example. The provided example can be implemented in ISE and it includes an address swap module that loops all received Ethernet packets back to the source after swapping the MAC source/destination addresses in the packet. The example design can be tested by connecting the ML505 board to the Ethernet socket of your PC and using the open source Wireshark software to monitor your Ethernet traffic. Read the Getting Started Guide for more details.
  • Simulation folderThe “simulation” folder contains testbenches for simulating the Ethernet MAC core example.

The Coregen folder for this tutorial can be downloaded in a compressed ZIP file. Please select the file corresponding to your board, right-click on it and select “Save Link As”.

Board Virtex-5 Version ZIP file
ML505 XC5VLX50T TEMACCore-ML505-v10-1.zip
ML506 XC5VSX50T TEMACCore-ML506-v10-1.zip
ML507 XC5VFX70T TEMACCore-ML507-v10-1.zip
ML509 XC5VLX110T TEMACCore-ML509-v10-1.zip

 

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Basic Coregen Tutorial

On October 18, 2008, in Core Generator, Version 10.1, by Jeff

Tutorial Overview

In this tutorial, we will generate a Multiplier IP core using the Xilinx CORE Generator version 10.1.

What will you learn

By following this tutorial, you will learn:

  • How to generate an IP core using the CORE Generator
  • What files are generated and how to use them

 

Requirements

Before following this tutorial, you will need to do the following:

  • Buy an ML505/ML506/ML507 or XUPV5 board if you don’t already have one. Xilinx supplies the ML50x boards, but the best deal is the XUPV5 from Digilent. Click the Digilent link for more information.

Create a Multiplier IP Core

Follow these steps to generate a Multiplier IP Core.

  1. From the “Start” menu, open Xilinx CORE Generator.
  2. Select “File->New Project”.
  3. Click “Browse” and select an appropriate location for a Coregen project. Within a Coregen project, you can create several cores that don’t necessarily relate to each other. Just select the folder where you normally place your projects, for example “C:\ML505\Projects”, and create a sub-folder called “Cores”. Open this folder and click “OK”.
  4. You will be asked for the specifications of the FPGA you are using. All the cores you generate under this CORE Generator project file will be customized for the FPGA you specify here. Under the “Part” tab, select these options: Family “Virtex5″, Device “xc5vlx50t”, Package “ff1136″, Speed grade “-1″. Click “OK”. Note: If you are not using the ML505 board, these specifications may not apply to you. You will have to enter the details corresponding to the specific FPGA that you are using.


    Under the “Generation” tab, you can specify how you want your IP cores to be generated. The tutorials on this website use VHDL, so be sure that it is selected as shown below. Also be sure that “NGC File” is selected, so that a .ngc netlist file is generated for your IP cores.

     

  5. When you have created your CORE Generator project, click on the “View by Function” tab to get a list of cores that you are able to generate.
  6. Open “Math Functions->Multipliers” and double-click on “Multiplier”.

     

  7. A dialog box should open to allow you to select the features of the Multiplier you want. For “Multiplier Type” select “Parallel Multiplier”. Select “Unsigned” for both port inputs and give them a width of 16 bits.

     

  8. Click “Finish”. Your Multiplier core will be generated and CORE Generator will display a list of all the generated files. Close this window, and close CORE Generator.

Examine the Generated Files

We will now examine the generated files and explain their purpose and utility. Different IP cores will be generated with a different set of files. It is always in your interest to examine the generated files when you generate an IP core, because you will often find useful documentation and examples. The types of files generated for the Multiplier core are common to other IP cores, however you can usually expect more files to be generated for more complex IP cores.

Open “Windows Explorer” and browse to the Coregen folder that we just created. We should see a list of files as shown below:

  • NGC Netlist File (multiplier.ngc)

    Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA.

     

  • VHDL Wrapper File (multiplier.vhd)

    VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core.

     

  • VHO Template File (multiplier.vho)

    VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design.

     

  • XCO CORE Generator Input File (multiplier.xco)

    CORE Generator input file containing the parameters used to regenerate a core.

     

  • File list (multiplier_flist.txt)

    Text file listing all of the output files produced when a customized core was generated in the CORE Generator.

     

  • XCO CORE Generator Input File (multiplier_mult_gen_v10_1_xst_1.ngc_xst.xrpt)

    Please see the core data sheet.

     

  • Readme File (multiplier_readme.txt)

    Text file indicating the files generated and how they are used.

     

  • ISE Project Navigator Interface File (multiplier_xmdf.tcl)

    ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project.

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Other Tutorials and Examples

On October 18, 2008, in Version 10.1, Xilinx Platform Studio (XPS), by Jeff

Here are links to some useful tutorials and examples hosted on other websites, including Xilinx:

Xilinx
EDK Concepts, Tools, and Techniques
A Hands-on Guide to Effective Embedded System Design

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