Did you know that the Zynq Ultrascale+ has 4 built-in Gigabit Ethernet MACs (GEMs)? That makes it awesome for Ethernet applications which is why I’ve just developed and shared an example design for the Zynq Ultrascale+ ZCU102 Evaluation board, armed with an Ethernet FMC to break-out those handy GEMs. The ZCU102 board has two FMC connectors, both high-pin-count (HPC), so I’ve created one basic design with two sets of constraints to choose from, depending on which FMC connector you want to use.

These scripts will build the Vivado project and block diagram for you: Zynq GEM Ethernet FMC example design

The scripts rely on the ZCU102 board definition files which don’t come built into Vivado 2016.1. I’m guessing that they will in the near future, but for now, to be able to build the project you’ll need to request access to the ZCU102 HeadStart Lounge and properly install the board definition files.

Want to know more about the Zynq UltraScale+ MPSoC? Checkout the video from Xilinx below. By the way, the image above comes from 0:58 of the video.

 

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

Facebook Twitter LinkedIn