Clocks, resets and wild goose chases

There’s a problem that I believe costs design companies billions of dollars a year whether they’re in hardware, software or FPGA design. The problem is hard to control, difficult to monitor and impossible to predict. The problem is bad design practice....

Is Xilinx losing to the competition?

I recently read an interesting article on Xilinx’s position with respect to its competitors: Is Xilinx Good Enough for You? As someone who works mainly with Xilinx FPGAs, I find it important to know how they are faring competitively. If one day a competitor...

The Virtex-6 based ML605

Forget about the ML505. The ML605 just made it obsolete. Not because of the Virtex-6 or the 8-lane PCIe or the DDR3… You need the ML605 because it has two FMC expansion connectors, one high-pin count and one low-pin count. You could do practically anything with...

How to read an NCD file

Sometimes we end up with two versions of the same design, where one works and one doesn’t work. If the code is the same, typically the problem is in placement of your primitives. In this case we would like to compare the two designs at a to find out what exactly...

Using SVN with HDL designs

Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs....