Code templates: Clock MUX

Let’s say we want to be able to switch dynamically between two (or more) clocks. In the Virtex FPGAs we have a primitive which allows us to do just this, it’s called the BUFGCTRL. The BUFGCTRL is a global clock buffer (like BUFG) which has two clock inputs...

Code templates: Generate for loop

This is the first part of a series of posts I will write on various code structures and examples for HDL designs. Here I want to talk about the generate statement and particularly the for loop. Most programmers think of a for loop as being a code segment that is...