Comments for FPGA Developer: Tools and tutorials for FPGA designers

Comment on FPGAs in High Frequency Trading by FPGAs: The software in the hardware « Software Trading

FPGAs: The software in the hardware « Software Trading — Sun, 12 Feb 2012 12:18:38 +0000

[...] The main benefit of FPGAs comes from reorganizing calculations. FPGAs work on a massively parallel basis. You get rid of bottlenecks in typical CPU design. While these bottlenecks are good for general purpose applications, like watching Pulp Fiction, they significantly slow down the amount of calculations that you do per second. In addition to being massively multi-parallel, FPGAs also are faster, according to FPGAdeveloper, because: [...]

Comment on Convert an ML505 EDK project for the XUPV5 by FlorianK

FlorianK — Fri, 10 Feb 2012 14:51:25 +0000

Hello,
i have the same Error, but i use a Virtex 5 FX30Tff665-3

Error Message:

Place:906 – Components driven by IO clock net can’t be placed and routed because location constraints are causing the clock region rules to be violated. IO Clock net is being driven by BUFIO locked to site “BUFIO_X0Y7″ Because of this location contraint, can only drive clock region “CLOCKREGION_X0Y1″. The following components driven by have been locked to sites outside of these clock regions:
DDR_memory_controller/DDR_memory_controller/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/dq_ce (Locked Site: ILOGIC_X0Y142 CLOCKREGION_X0Y3)
DDR_memory_controller/DDR_memory_controller/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/dq_ce (Locked Site: ILOGIC_X0Y142 CLOCKREGION_X0Y3)
Please evaluate the location constraints of both the BUFIO and the components driven by to ensure that they follow the clock region rules of the architecture. For more information on the clock region rules, please refer to the architecture user’s guide. To debug your design with partially routed design, please allow mapper/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

My UCF-File looks like this (it is only that Part which i think i have to modify):

###############################################################################
# LOC placement of DQS-squelch related IDDR and IDELAY elements
# Each circuit can be located at any of the following locations:
# 1. Unused “N”-side of DQS differential pair I/O
# 2. DM data mask (output only, input side is free for use)
# 3. Any output-only site
###############################################################################

###############################################################################
#The following constraint is added to avoid the HOLD violations in the trace report
#when run for unconstrained paths.These two FF groups will be clocked by two different
# clocks and hence there should be no timing analysis performed on this path.
###############################################################################
#INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/u_phy_calib_0/gen_gate[*].u_en_dqs_ff” TNM = EN_DQS_FF;
#TIMESPEC TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = FROM EN_DQS_FF TO TNM_DQ_CE_IDDR 3.85 ns DATAPATHONLY;

INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce” LOC = “ILOGIC_X0Y142″;
INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce” LOC = “IODELAY_X0Y142″;
INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce” LOC = “ILOGIC_X0Y140″;
INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce” LOC = “IODELAY_X0Y140″;
INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce” LOC = “ILOGIC_X0Y138″;
INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce” LOC = “IODELAY_X0Y138″;
INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce” LOC = “ILOGIC_X0Y102″;
INST “*/DDR_memory_controller/mpmc_core_0/gen_??_ddr2_phy.mpmc_phy_if_0/u_phy_io*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce” LOC = “IODELAY_X0Y102″;

###############################################################################
# LOC and timing constraints for flop driving DQS CE enable signal
# from fabric logic. Even though the absolute delay on this path is
# calibrated out (when synchronizing this output to DQS), the delay
# should still be kept as low as possible to reduce post-calibration
# voltage/temp variations – these are roughly proportional to the
# absolute delay of the path.
# The following code has been commented for V5 as the predictable IP will take
# care of placement of these flops by meeting the MAXDELAY requirement.
# These constraints will be removed in the next release.
###############################################################################

INST “*/u_phy_calib_0/gen_gate[0].u_en_dqs_ff” LOC = “SLICE_X0Y71″;
INST “*/u_phy_calib_0/gen_gate[1].u_en_dqs_ff” LOC = “SLICE_X0Y70″;
INST “*/u_phy_calib_0/gen_gate[2].u_en_dqs_ff” LOC = “SLICE_X0Y69″;
INST “*/u_phy_calib_0/gen_gate[3].u_en_dqs_ff” LOC = “SLICE_X0Y51″;

Can pls someone explaining me how can i correct this Part?
Thx FlorianK

Comment on Tutorials by evg

evg — Fri, 10 Feb 2012 14:14:56 +0000

I am also interested in tutorials about ML605 & FMC150 card. For a while I am trying to get the signal from the FMC board but it is not successful. I know that there is the easiest way to do it but I still didn’t get it. I will be grateful for the help!

Comment on Read DIP switches from a Microblaze application by amin

amin — Sun, 29 Jan 2012 16:31:05 +0000

hi
thanks a lot for this post.
i start work with fpga an microblaze for image processing.
i want to participate with other prson that work in this area.
sirkhazaei@gmail.com

Comment on Creating a project using the Base System Builder by Hardik Shah

Hardik Shah — Sun, 29 Jan 2012 07:36:02 +0000

Thanks a lot!
It is these things that help amateur beginners like us to prevent ourselves from getting lost in the complicated maze of the functions that the EDK & SDK provide.

Comment on Convert Bit Files to System ACE Files by cousteau

cousteau — Mon, 23 Jan 2012 17:33:08 +0000

Nice entry. Although it’s not necessary to make the batch script; I’d rather just type
xmd -tcl ./genace.tcl -jprog -hw download.bit -board ml505 -ace MYDESIGN.ACE
on a bash/cmd terminal.

Comment on How to keep a signal name after mapping by juangagobenitez

juangagobenitez — Fri, 20 Jan 2012 12:43:54 +0000

Your post has been very helpfully to me, thanks!

Comment on Tutorials by mark

mark — Thu, 05 Jan 2012 19:27:33 +0000

Will there be any tutorials on the ML605? I am interested in using the 4DSP FMC150 ADC/DAC card

Comment on Tutorials by Pieter Taelman

Pieter Taelman — Thu, 29 Dec 2011 20:30:57 +0000

Hello,

I was wondering if it is possible to implement threading on Microblaze? (pthreads,..).

How do you make a big system? I have to make a robot, controlled by a Microblaze processor. A wireless Xbee module (RS232, i used UartLite on Microblaze) sends commands to my microblaze processor. But how can i execute my received commands. I think it is not good to run all the logic in one thread.

Comment on Tutorials by Saravan

Saravan — Thu, 29 Dec 2011 06:15:56 +0000

Thanxs, your tutorials are very useful to me.please try to give software application c codes for ETHERNET Applications using ml507 FPGA Board.