https://www.fpgadeveloper.com/boards/ Recent content in Boards on FPGA Developer Hugo -- gohugo.io jeff@fpgadeveloper.com (Jeff Johnson) jeff@fpgadeveloper.com (Jeff Johnson) Mon, 02 Dec 2024 00:00:00 +0000 https://www.fpgadeveloper.com/boards/vek280/ Mon, 02 Dec 2024 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vek280/ https://www.fpgadeveloper.com/boards/vck190/ Tue, 08 Oct 2024 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vck190/ Useful Links AMD Versal AI Core Series VCK190 Evaluation Kit Product Page Device Versal™ AI Core XCVC1902-2MSEVSVA2197 Adaptive SoC VADJ The board has a Zynq UltraScale+ device that acts as the system controller. On power up, the system controller reads FRU data on the EEPROM of the connected FMC card, and sets the VADJ voltage accordingly. Supported VADJ voltages are 1.2V and 1.5V. Versal Configuration Boot mode of the Versal device is determined by DIP switch SW1. https://www.fpgadeveloper.com/boards/vmk180/ Tue, 08 Oct 2024 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vmk180/ Useful Links AMD Versal Prime Series VMK180 Evaluation Kit Product Page Device Versal™ Prime XCVM1802-2MSEVSVA2197 Adaptive SoC VADJ The board has a Zynq UltraScale+ device that acts as the system controller. On power up, the system controller reads FRU data on the EEPROM of the connected FMC card, and sets the VADJ voltage accordingly. Supported VADJ voltages are 1.2V and 1.5V. Versal Configuration Boot mode of the Versal device is determined by DIP switch SW1. https://www.fpgadeveloper.com/boards/vpk120/ Tue, 08 Oct 2024 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vpk120/ https://www.fpgadeveloper.com/boards/zcu104/ Wed, 12 Jul 2023 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zcu104/ Useful Links Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit Product Page Device Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC VADJ The onboard System Controller reads FRU data on the EEPROM of the connected FMC card, and sets the VADJ voltage accordingly. Configuration Boot mode is determined by DIP switch SW6. SW6 1 2 3 4 JTAG (default) 1 1 1 1 QSPI32 1 0 1 1 SD 1 0 0 0 https://www.fpgadeveloper.com/boards/zcu106/ Thu, 15 Jun 2023 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zcu106/ Useful Links Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit Product Page Device Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC VADJ The onboard System Controller reads FRU data on the EEPROM of the connected FMC card, and sets the VADJ voltage accordingly. Configuration Boot mode is determined by DIP switch SW6. SW6 1 2 3 4 JTAG (default) 1 1 1 1 QSPI32 1 0 1 1 SD 1 0 0 0 https://www.fpgadeveloper.com/boards/kria-kv260/ Fri, 11 Nov 2022 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/kria-kv260/ https://www.fpgadeveloper.com/boards/ac701/ Sat, 01 May 2021 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/ac701/ Useful Links Artix®-7 FPGA AC701 Evaluation Kit Product Page Device Artix®-7 XC7A200T-2FBG676C FPGA Configuration FPGA configuration is determined by DIP switch SW1. Config mode 1 2 3 JTAG 1 X 1 Master SPI 0 X 1 Notes: Switch 2 is not used X = don’t care 0 = OFF position 1 = ON position https://www.fpgadeveloper.com/boards/kc705/ Sat, 01 May 2021 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/kc705/ Useful Links Kintex®-7 FPGA KC705 Evaluation Kit Product Page Device Kintex®-7 XC7K325T-2FFG900C FPGA Configuration FPGA configuration is determined by DIP switch SW13. Config mode 1 2 3 4 5 JTAG X X 1 0 1 Master BPI Note 4 Note 4 0 1 0 Quad SPI X X 0 0 1 Notes: X = don’t care 0 = OFF position 1 = ON position Switches 1 and 2 are A25 and A24 respectively and determine which of 4 bitstreams is booted from the Linear BPI flash https://www.fpgadeveloper.com/boards/kcu105/ Sat, 01 May 2021 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/kcu105/ Useful Links Kintex UltraScale FPGA KCU105 Evaluation Kit Product Page Device Kintex® UltraScale™ XCKU040-2FFVA1156E FPGA Configuration FPGA configuration is determined by DIP switch SW15. Config mode 1 2 3 4 5 6 JTAG X X X X 0 1 JTAG SD X X X X 1 1 Quad SPI Note 4 Note 4 Note 4 Note 4 0 0 Notes: https://www.fpgadeveloper.com/boards/vc707/ Sat, 01 May 2021 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vc707/ Useful Links Virtex-7 FPGA VC707 Evaluation Kit Product Page Device Virtex-7 XC7VX485T-2FFG1761 FPGA Configuration FPGA configuration is determined by DIP switch SW11. Config mode 1 2 3 4 5 Master BPI Note 4 Note 4 0 1 0 JTAG (independent) X X 1 0 1 Notes: X = don’t care 0 = OFF position 1 = ON position Switches 1 and 2 are A25 and A24 respectively and determine which of 4 bitstreams is booted from the Linear BPI flash https://www.fpgadeveloper.com/boards/vc709/ Sat, 01 May 2021 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vc709/ Useful Links Virtex-7 FPGA VC709 Evaluation Kit Product Page Device Virtex-7 XC7VX690T-2FFG1761C FPGA Configuration FPGA configuration is determined by DIP switch SW11. Config mode 1 2 3 4 5 Master BPI Note 4 Note 4 0 1 0 JTAG (independent) X X 1 0 1 Notes: X = don’t care 0 = OFF position 1 = ON position Switches 1 and 2 are A25 and A24 respectively and determine which of 4 bitstreams is booted from the Linear BPI flash https://www.fpgadeveloper.com/boards/vcu108/ Sat, 01 May 2021 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vcu108/ Useful Links Xilinx Virtex UltraScale FPGA VCU108 Evaluation Kit Product Page Device Virtex® UltraScale™ XCVU095-2FFVA2104E FPGA VADJ An onboard system controller reads FRU data on the EEPROM of the connected FMC card, and sets the VADJ voltage accordingly. Supported VADJ voltages are 1.2V, 1.5V and 1.8V. Configuration Boot mode is determined by DIP switch SW16. Config mode 1 2 3 4 5 Master BPI x x 0 1 0 JTAG x x 1 0 1 Switches 1 and 2 determine which of four possible configuration bitstreams to load from Master BPI flash. https://www.fpgadeveloper.com/boards/vcu118/ Sat, 01 May 2021 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/vcu118/ Useful Links Xilinx Virtex UltraScale+ FPGA VCU118 Evaluation Kit Product Page Device Virtex® UltraScale+™ XCVU9P-L2FLGA2104E FPGA VADJ An onboard system controller reads FRU data on the EEPROM of the connected FMC card, and sets the VADJ voltage accordingly. Supported VADJ voltages are 1.2V, 1.5V and 1.8V. Configuration Boot mode is determined by DIP switch SW16. Config mode 1 2 3 4 Master SPI x 0 0 1 JTAG x 1 0 1 https://www.fpgadeveloper.com/boards/ultra96/ Wed, 16 Dec 2020 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/ultra96/ Useful Links Ultra96 Product Page Ultra96 Board Definition Files Device Zynq™ UltraScale+ MPSoC ZU3EG A484 Configuration Boot mode is determined by DIP switch labelled SW2. Boot mode 1 2 JTAG 1 1 SD Card 0 1 USB 0 0 Notes: 0 = OFF 1 = ON https://www.fpgadeveloper.com/boards/96b-quad-ethernet/ Thu, 10 Dec 2020 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/96b-quad-ethernet/ Useful Links 96B Quad Ethernet Mezzanine Product Page 96B Quad Ethernet Mezzanine Documentation https://www.fpgadeveloper.com/boards/fpga-drive-fmc/ Mon, 02 Dec 2019 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/fpga-drive-fmc/ Useful Links FPGA Drive FMC Purchase Page FPGA Drive FMC Product Page https://www.fpgadeveloper.com/boards/myd-y7z010/ Fri, 04 May 2018 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/myd-y7z010/ https://www.fpgadeveloper.com/boards/pynq-z1/ Fri, 20 Apr 2018 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/pynq-z1/ Useful Links PYNQ-Z1 Product Page PYNQ-Z1 Board Definition Files Device Zynq™-7000 SoC XC7Z020-1CLG400C https://www.fpgadeveloper.com/boards/ethernet-fmc/ Sat, 17 Mar 2018 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/ethernet-fmc/ Useful Links Ethernet FMC Purchase Page Ethernet FMC Product Page Ethernet FMC Documentation https://www.fpgadeveloper.com/boards/arty-a7/ Wed, 15 Nov 2017 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/arty-a7/ Useful Links Arty A7 Product Page Arty A7 Board Definition Files Device Arty A7-35T: Artix®-7 XC7A35TICSG324-1L FPGA Arty A7-100T: Artix®-7 XC7A100TCSG324-1 FPGA https://www.fpgadeveloper.com/boards/microzed/ Wed, 01 Nov 2017 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/microzed/ Useful Links MicroZed Product Page MicroZed Board Definition Files Device MicroZed 7010: Zynq™-7000 SoC XC7Z010-1CLG400C MicroZed 7020: Zynq™-7000 SoC XC7Z020-1CLG400C Configuration Boot mode is determined by jumper headers labelled JP3, JP2 and JP1. Boot mode JP3 JP2 JP1 JTAG (cascaded) 0 0 0 JTAG (independent) 0 0 1 Quad-SPI 1 0 X SD Card 1 1 X Notes: https://www.fpgadeveloper.com/boards/ultrazed/ Tue, 24 Oct 2017 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/ultrazed/ Useful Links UltraZed-EG Product Page UltraZed-EG Board Definition Files Device UltraZed-EG: Zynq™ UltraScale+ MPSoC XZU3EG-1SFVA625E Configuration Boot mode is determined by DIP switch labelled SW2. Boot mode 1 2 3 4 JTAG 1 1 1 1 Quad-SPI24 0 1 1 1 Quad-SPI32 1 0 1 1 SD Card 0 1 0 1 EMMC18 1 0 0 1 SD Card 1 0 0 0 Notes: https://www.fpgadeveloper.com/boards/z-turn/ Wed, 18 Oct 2017 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/z-turn/ Useful Links Z-Turn Product Page Z-Turn Board Definition Files Device Zynq™-7000 SoC XC7Z010-1CLG400 https://www.fpgadeveloper.com/boards/picozed/ Sat, 02 Jul 2016 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/picozed/ Useful Links PicoZed Product Page PicoZed Board Definition Files Device PicoZed 7010: Zynq™-7000 SoC XC7Z010-1CLG400 PicoZed 7015: Zynq™-7000 SoC XC7Z015-1CLG485 PicoZed 7020: Zynq™-7000 SoC XC7Z020-1CLG400 PicoZed 7030: Zynq™-7000 SoC XC7Z030-1SBG485 Configuration Boot mode is determined by DIP switch labelled SW1. Boot mode 1 2 JTAG 0 0 Quad-SPI 0 1 SD Card 1 1 Notes: https://www.fpgadeveloper.com/boards/zcu102/ Fri, 17 Jun 2016 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zcu102/ Useful Links Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit Product Page Device Zynq UltraScale+ XCZU9EG-2FFVB1156 MPSoC VADJ The onboard MSP430 System Controller reads FRU data on the EEPROM of the connected FMC card, and sets the VADJ voltage accordingly. Configuration Boot mode is determined by DIP switch SW6. SW6 1 2 3 4 JTAG (default) 1 1 1 1 QSPI32 1 0 1 1 SD 1 0 0 0 https://www.fpgadeveloper.com/boards/zedboard/ Wed, 04 May 2016 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zedboard/ Useful Links ZedBoard Product Page ZedBoard Board Definition Files are built into Vivado Device Zynq™-7000 SoC XC7Z020-CLG484-1 VADJ The VADJ voltage is determined by jumper header J18 and can be manually set to 1.8V, 2.5V or 3.3V. Configuration Boot mode is determined by jumper headers labelled MIO2-MIO6. Boot mode MIO6 MIO5 MIO4 MIO3 MIO2 JTAG (cascaded) X 0 0 0 0 JTAG (independent) X 0 0 0 1 Quad-SPI X 1 0 0 X SD Card X 1 1 0 X Notes: https://www.fpgadeveloper.com/boards/mars-zx3/ Mon, 18 May 2015 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/mars-zx3/ https://www.fpgadeveloper.com/boards/te0720/ Mon, 18 May 2015 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/te0720/ https://www.fpgadeveloper.com/boards/zynq-mmp/ Mon, 18 May 2015 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zynq-mmp/ EOL This board is in End of Life. Useful Links Zynq MMP Product Page Device Zynq™-7000 SoC XC7Z045-1FFG900 Zynq™-7000 SoC XC7Z100-2FFG900 https://www.fpgadeveloper.com/boards/serdes-fmc/ Mon, 06 Oct 2014 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/serdes-fmc/ The SERDES FMC was Opsero’s first FMC card designed to provide gigabit transceivers on FPGA/SoC dev boards that didn’t have any (such as the ZedBoard). As a design it was a great success, but unfortunately there wasn’t much demand for this as a product, so we never put it into production. https://www.fpgadeveloper.com/boards/zc706/ Wed, 12 Mar 2014 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zc706/ Useful Links Zynq®-7000 ZC706 Evaluation Kit Product Page Device Zynq®-7000 XC7Z045 FFG900 – 2 SoC Configuration Boot mode is determined by DIP switch SW11. SW11 1 2 3 4 5 JTAG (default) 0 0 0 0 0 JTAG (independent) 1 0 0 0 0 QSPI 0 0 0 1 0 SD 0 0 1 1 0 https://www.fpgadeveloper.com/boards/zynq-mini-itx/ Tue, 04 Mar 2014 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zynq-mini-itx/ Useful Links Mini-ITX Board Product Page Device Zynq™-7000 SoC XC7Z045-2FFG900 Zynq™-7000 SoC XC7Z100-2FFG900 https://www.fpgadeveloper.com/boards/zc702/ Tue, 04 Mar 2014 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zc702/ Useful Links Zynq®-7000 ZC702 Evaluation Kit Product Page Device Zynq®-7000 XC7Z020-CLG484-1 Configuration Boot mode is determined by DIP switch SW16. SW16 1 2 3 4 5 JTAG (default) 0 0 0 0 0 JTAG (independent) 1 0 0 0 0 QSPI 0 0 0 1 0 SD 0 0 1 1 0 https://www.fpgadeveloper.com/boards/zybo/ Tue, 04 Mar 2014 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/zybo/ Useful Links Zybo Z7 Product Page Zybo Z7 Board Definition Files Device Zybo Z7-10: Zynq™-7000 SoC XC7Z010-1CLG400 Zybo Z7-20: Zynq™-7000 SoC XC7Z020-1CLG400 https://www.fpgadeveloper.com/boards/ml505-xupv5/ Tue, 05 Jul 2011 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/ml505-xupv5/ https://www.fpgadeveloper.com/boards/ml605/ Fri, 01 Jul 2011 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/ml605/ https://www.fpgadeveloper.com/boards/xupv2p/ Sun, 19 Oct 2008 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/xupv2p/ https://www.fpgadeveloper.com/boards/ultrazed-ev/ Mon, 01 Jan 0001 00:00:00 +0000 jeff@fpgadeveloper.com (Jeff Johnson) https://www.fpgadeveloper.com/boards/ultrazed-ev/ Useful Links UltraZed-EV Product Page UltraZed-EV Board Definition Files Device UltraZed-EV: Zynq™ UltraScale+ MPSoC XCZU7EV-1FBVB900E Configuration Boot mode is determined by DIP switch labelled SW2. Boot mode 1 2 3 4 JTAG 1 1 1 1 Quad-SPI24 0 1 1 1 Quad-SPI32 1 0 1 1 SD1/MMC33 0 1 0 1 SD1/MMC33 1 0 0 0 EMMC18 1 0 0 1 Notes: