<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Zynq on FPGA Developer</title><link>https://www.fpgadeveloper.com/tags/zynq/</link><description>Recent content in Zynq on FPGA Developer</description><generator>Hugo</generator><language>en</language><copyright>Copyright (c) 2024-2026 FPGA Developer</copyright><lastBuildDate>Fri, 04 May 2018 00:00:00 +0000</lastBuildDate><atom:link href="https://www.fpgadeveloper.com/tags/zynq/index.xml" rel="self" type="application/rss+xml"/><item><title>Board bring-up: MYIR MYD-Y7Z010 Dev board</title><link>https://www.fpgadeveloper.com/2018/05/board-bring-up-myir-myd-y7z010-dev-board.html</link><pubDate>Fri, 04 May 2018 00:00:00 +0000</pubDate><guid>https://www.fpgadeveloper.com/2018/05/board-bring-up-myir-myd-y7z010-dev-board.html</guid><description>Bringing up the 3 Gigabit Ethernet ports on the MYIR MYD-Y7Z010 with Vivado and SDK</description></item><item><title>Creating a custom AXI-Streaming IP in Vivado</title><link>https://www.fpgadeveloper.com/2017/11/creating-a-custom-axi-streaming-ip-in-vivado.html</link><pubDate>Wed, 01 Nov 2017 00:00:00 +0000</pubDate><guid>https://www.fpgadeveloper.com/2017/11/creating-a-custom-axi-streaming-ip-in-vivado.html</guid><description>Step-by-step tutorial for building a custom AXI-Streaming FIFO IP in Vivado and testing it with DMA</description></item><item><title>Getting Started with the MYIR Z-turn</title><link>https://www.fpgadeveloper.com/2017/10/getting-started-with-the-myir-z-turn.html</link><pubDate>Wed, 18 Oct 2017 00:00:00 +0000</pubDate><guid>https://www.fpgadeveloper.com/2017/10/getting-started-with-the-myir-z-turn.html</guid><description>Creating a Vivado design for the MYIR Z-turn Zynq SoM and running hello world and lwIP echo server</description></item><item><title>ZynqBoard: The World's Smallest Zynq SoM</title><link>https://www.fpgadeveloper.com/2016/03/zynqboard-the-worlds-smallest-zynq-som.html</link><pubDate>Fri, 11 Mar 2016 00:00:00 +0000</pubDate><guid>https://www.fpgadeveloper.com/2016/03/zynqboard-the-worlds-smallest-zynq-som.html</guid><description>Reviewing ZynqBoard, a minimal 42x22mm Zynq SoM stripped down to only the essentials.</description></item><item><title>Creating a Base System for the Zynq in Vivado</title><link>https://www.fpgadeveloper.com/2014/07/creating-a-base-system-for-the-zynq-in-vivado.html</link><pubDate>Thu, 31 Jul 2014 00:00:00 +0000</pubDate><guid>https://www.fpgadeveloper.com/2014/07/creating-a-base-system-for-the-zynq-in-vivado.html</guid><description>Step-by-step tutorial for building a base Zynq design in Vivado using the MicroZed board.</description></item><item><title>Zynq and the trend towards ARM-FPGA architectures</title><link>https://www.fpgadeveloper.com/2014/06/zynq-trend-towards-arm-fpga.html</link><pubDate>Mon, 16 Jun 2014 00:00:00 +0000</pubDate><guid>https://www.fpgadeveloper.com/2014/06/zynq-trend-towards-arm-fpga.html</guid><description>Why the Zynq SoC is popular and what the ARM+FPGA trend means for the industry</description></item><item><title>Create an application using the Xilinx SDK</title><link>https://www.fpgadeveloper.com/2014/02/create-an-application-using-the-sdk.html</link><pubDate>Thu, 27 Feb 2014 00:00:00 +0000</pubDate><guid>https://www.fpgadeveloper.com/2014/02/create-an-application-using-the-sdk.html</guid><description>Tutorial on creating a hello-world application for the Zynq ARM processor using Xilinx SDK</description></item></channel></rss>