<?xml version="1.0" encoding="utf-8" standalone="yes"?><urlset xmlns="http://www.sitemaps.org/schemas/sitemap/0.9" xmlns:xhtml="http://www.w3.org/1999/xhtml"><url><loc>https://www.fpgadeveloper.com/how-to-build-the-hardware-platform-for-certified-ubuntu-20.04-lts-for-zcu106/</loc><lastmod>2023-05-19T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/processorless-ethernet-part-3/</loc><lastmod>2021-05-01T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/processorless-ethernet-part-2/</loc><lastmod>2021-04-20T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/driving-ethernet-ports-without-a-processor/</loc><lastmod>2021-02-16T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/how-to-program-configuration-flash-with-vivado-hardware-manager/</loc><lastmod>2021-01-18T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2018/05/board-bring-up-myir-myd-y7z010-dev-board.html</loc><lastmod>2018-05-04T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2018/03/how-to-accelerate-a-python-function-with-pynq.html</loc><lastmod>2018-03-22T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2018/03/create-a-custom-pynq-overlay-for-pynq-z1.html</loc><lastmod>2018-03-15T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2017/11/artix-7-arty-base-project.html</loc><lastmod>2017-11-08T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2017/11/creating-a-custom-axi-streaming-ip-in-vivado.html</loc><lastmod>2017-11-01T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2017/10/getting-started-with-the-myir-z-turn.html</loc><lastmod>2017-10-18T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2017/10/using-axi-dma-in-vivado-reloaded.html</loc><lastmod>2017-10-11T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2016/11/tcl-automation-tips-for-vivado-xilinx-sdk.html</loc><lastmod>2016-11-01T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2016/05/multi-port-ethernet-in-petalinux.html</loc><lastmod>2016-05-04T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2016/04/connecting-an-ssd-to-an-fpga-running-petalinux.html</loc><lastmod>2016-04-15T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2016/04/zynq-pci-express-root-complex-design-in-vivado.html</loc><lastmod>2016-04-14T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2016/04/microblaze-pci-express-root-complex-design-in-vivado.html</loc><lastmod>2016-04-13T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2016/01/running-a-lwip-echo-server-on-a-multi-port-ethernet-design.html</loc><lastmod>2016-01-05T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2015/12/fpga-network-tap-designing-ethernet-pass-through.html</loc><lastmod>2015-12-29T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2015/12/using-axi-ethernet-subsystem-and-gmii-to-rgmii-in-a-multi-port-ethernet-design.html</loc><lastmod>2015-12-08T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html</loc><lastmod>2014-08-06T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html</loc><lastmod>2014-08-04T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2014/08/version-control-for-vivado-projects.html</loc><lastmod>2014-08-01T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url><url><loc>https://www.fpgadeveloper.com/2014/07/creating-a-base-system-for-the-zynq-in-vivado.html</loc><lastmod>2014-07-31T00:00:00+00:00</lastmod><changefreq>monthly</changefreq><priority>0.5</priority></url></urlset>