Entrepreneurial

Announcing that the new Ethernet FMC, a Quad Gigabit Ethernet FPGA Mezzanine Card (FMC) is now available to buy. The board is designed for easy integration with the ZedBoard, with open-source example designs so you can start designing your product sooner. The low-pin-count FMC features 4 Marvell PHYs, a 125MHz oscillator and a quad RJ45 with integrated magnetics.

The Ethernet FMC is compliant to the Vita 57.1 FMC standard except for its height (due to the RJ45 connector) and its length. The FMC is electrically and mechanically compatible with the ZedBoard and all the Xilinx evaluation boards.

Here’s the next product in Opsero’s growing lineup of FPGA I/O cards: the Quad Gigabit Ethernet FMC. This low-pin-count FMC is loaded with four Marvell Gigabit Ethernet PHYs and enables FPGA networking applications on the ZedBoard and other LPC carriers. A demo design for the ZedBoard is available on Github at the link below and further demos will become available in the next few weeks:

https://github.com/fpgadeveloper/zedboard-qgige

Look out for more details including the technical specs, schematics and more on the soon to be launched product page. (Update 2014-11-06: the product page is now open)

Here’s a peek at the first units of the SERDES FMCs, the first low pin-count FPGA Mezzanine Card to enable multi-gigabit transceivers on the ZedBoard and other FPGA boards that don’t have internal MGTs. The first board is designed for SFP modules for Ethernet and optical applications whereas the second board has SATA connectors for custom applications. Both boards are compliant to the VITA 57 standard.

Stay tuned for the performance results this week!

Yesterday I received the bare PCBs for the SERDES SFP FMC, my new product that enables 2 multi-gigabit transceivers on the ZedBoard or other LPC FMC carriers that don’t have internal MGTs.

In the last couple of weeks I’ve been working hard on a demo design in Vivado which you can find on Github here:

https://github.com/fpgadeveloper/zedboard-serdes-sfp-fmc

So far all timing passes at the board’s top speed of 3.125Gbps (or 2.5Gbps with DC balanced encoding).

After years designing products for other companies, I’ve finally designed something for my own company.

If you have a ZedBoard and you want to experiment with MGTs, now you can with my two new SERDES low-pin-count FMCs. Both boards use the DS32EL0421/DS32EL0124 serializer/deserializer devices from Texas Instruments to provide two external multi-gigabit transceivers from any standard FMC carrier regardless of whether the FPGA has internal MGTs or not. The external MGTs can transmit and receive data up to 2.5Gbps with DC-balance encoding (8b/10b) or up to 3.125Gbps without DC-balance encoding.

I’m now fully committed to consulting through my new company: Opsero Electronic Design.

I’m offering FPGA design services including:

• HDL Programming
• IP core design
• EDK/ISE project design
• Design modification
• Simulation
• Hardware verification
• Debugging
• Timing closure

I’m also offering electronic hardware design services including:

• System architecture design
• Analog, digital and mixed circuits
• Parts selection
• Schematic capture
• Verification through SPICE simulation
• SPICE model creation
• PCB layout

If you need a consultant for any of the above services, don’t hesitate to contact me through my company website.

I’ve left my full-time job to start a business in electronics consulting! It feels good to finally follow my dream.

I’m asking my readers for help in choosing a company name, please vote!

Update 9-7-2013: The voting is closed. Opsero wins by 2 votes! Thanks to everyone who voted!

Some of you will know that I ran some polls on the site over the last couple of months. Well I checked out the results and accordingly there will be some big changes on the site, the first of which is that I’ve moved to WordPress and given the site a fresh new look.

Thanks to all the people who responded to the polls, your input was very very appreciated! Here are the changes: