Below we describe various problems with the XUPV2P board and/or XPS software, and the solution or work-around.

No Vista Support for 9.1 or Older
Presently, the EDK and ISE platforms versions 9.1 and older do not support Vista. You must upgrade to version 9.2 to operate under Vista.

The Onewire Problem

Conditions I am using the Digilent XUPV2P board with Xilinx Platform Studio v8.2i. I connect to my XUPV2P board via USB (i.e. not JTAG).
Problem I have a working project but for some reason, it does not work if it is the first project to be downloaded to the XUPV2P after the power is turned ON. To make it work, I download another project to the XUPV2P after power-up, then I download the project I want to use.
Peculiarities Not all my projects have this problem. It seems to be the more complex projects, such as those using the RocketIO MGTs.
Our Solution and Observations When you create your more complex projects using the Base System Builder, be sure to always include the “Onewire_0” interface, even if you don’t need it. Your projects will work even after the XUPV2P board is powered up. Strangely, for simple projects, including the “Onewire_0” interface will actually make it fail to work after power-up.

This problem can be reproduced by following through the tutorial: Create an Oscillator with a RocketIO MGT. Follow the tutorial and leave out the “Onewire_0” interface. You will find that the project does not work if it is the first project to be downloaded after the XUPV2P board is powered up.

To reproduce the inverse problem for simple projects, try creating a project using Base System Builder and include the “Onewire_0” and “RS232” interfaces only. Include the default peripheral test application, then generate and download the bitstream. You will find that this project will not work if it is the first to be downloaded to the FPGA after power-up. Remove the “Onewire_0” interface manually and you will find that the project will now work.

At present, we have not managed to trace the source of this problem, nor do we understand why our solution actually works. If you know why this problem exists or why the solution works, leave a comment please!

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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