Tutorial Overview

In this tutorial, we will generate a Multiplier IP core using the Xilinx CORE Generator version 10.1.

What will you learn

By following this tutorial, you will learn:

  • How to generate an IP core using the CORE Generator
  • What files are generated and how to use them



Before following this tutorial, you will need to do the following:

  • Buy an ML505/ML506/ML507 or XUPV5 board if you don’t already have one. Xilinx supplies the ML50x boards, but the best deal is the XUPV5 from Digilent. Click the Digilent link for more information.

Create a Multiplier IP Core

Follow these steps to generate a Multiplier IP Core.

  1. From the “Start” menu, open Xilinx CORE Generator.
  2. Select “File->New Project”.
  3. Click “Browse” and select an appropriate location for a Coregen project. Within a Coregen project, you can create several cores that don’t necessarily relate to each other. Just select the folder where you normally place your projects, for example “C:\ML505\Projects”, and create a sub-folder called “Cores”. Open this folder and click “OK”.
  4. You will be asked for the specifications of the FPGA you are using. All the cores you generate under this CORE Generator project file will be customized for the FPGA you specify here. Under the “Part” tab, select these options: Family “Virtex5”, Device “xc5vlx50t”, Package “ff1136”, Speed grade “-1”. Click “OK”. Note: If you are not using the ML505 board, these specifications may not apply to you. You will have to enter the details corresponding to the specific FPGA that you are using.

    Under the “Generation” tab, you can specify how you want your IP cores to be generated. The tutorials on this website use VHDL, so be sure that it is selected as shown below. Also be sure that “NGC File” is selected, so that a .ngc netlist file is generated for your IP cores.


  5. When you have created your CORE Generator project, click on the “View by Function” tab to get a list of cores that you are able to generate.
  6. Open “Math Functions->Multipliers” and double-click on “Multiplier”.


  7. A dialog box should open to allow you to select the features of the Multiplier you want. For “Multiplier Type” select “Parallel Multiplier”. Select “Unsigned” for both port inputs and give them a width of 16 bits.


  8. Click “Finish”. Your Multiplier core will be generated and CORE Generator will display a list of all the generated files. Close this window, and close CORE Generator.

Examine the Generated Files

We will now examine the generated files and explain their purpose and utility. Different IP cores will be generated with a different set of files. It is always in your interest to examine the generated files when you generate an IP core, because you will often find useful documentation and examples. The types of files generated for the Multiplier core are common to other IP cores, however you can usually expect more files to be generated for more complex IP cores.

Open “Windows Explorer” and browse to the Coregen folder that we just created. We should see a list of files as shown below:

  • NGC Netlist File (multiplier.ngc)

    Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA.


  • VHDL Wrapper File (multiplier.vhd)

    VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core.


  • VHO Template File (multiplier.vho)

    VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design.


  • XCO CORE Generator Input File (multiplier.xco)

    CORE Generator input file containing the parameters used to regenerate a core.


  • File list (multiplier_flist.txt)

    Text file listing all of the output files produced when a customized core was generated in the CORE Generator.


  • XCO CORE Generator Input File (multiplier_mult_gen_v10_1_xst_1.ngc_xst.xrpt)

    Please see the core data sheet.


  • Readme File (multiplier_readme.txt)

    Text file indicating the files generated and how they are used.


  • ISE Project Navigator Interface File (multiplier_xmdf.tcl)

    ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project.

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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