Tutorial Overview

In some FPGA designs, it is necessary to interface two devices that operate in different clock domains. One solution to crossing from one clock domain to another is by using FIFOs with independent read and write clocks. In this tutorial, we will generate FIFOs with independent read and write clocks, and non-symmetric aspect ratios.

This tutorial was written for the Aurora to Ethernet Bridge project in which we want to interface the Ethernet MAC to the Aurora core. The Ethernet MAC has a data interface that is 8 bits wide and clocked at 125MHz. The Aurora core has a data interface that is 16 bits wide and clocked at 62.5MHz. The two clocks (125MHz and 62.5MHz) are derived from the same reference clock, so they will be synchronized and we will not have to perform any clock correction. Our only problems are crossing the clock domains and interfacing the non-symmetric data widths (8/16 bits).

To solve our problem, we will use two FIFOs with independent read and write clocks and non-symmetric aspect ratios. We will have to generate one FIFO for each direction of data flow. The first FIFO will need an input width of 16 bits and an output width of 32 bits (for the EMAC RX to Aurora TX connection). The second FIFO will need an input width of 32 bits and an output width of 16 bits (for the Aurora RX to EMAC TX connection). We have chosen to use double the data width in all cases because we are dealing with frame data and so we also need to transfer the Start of Frame (SOF) and End of Frame (EOF) bits.

Requirements

All you will need to generate the clock domain crossing FIFO is CORE Generator from Xilinx.

Generate a CORE Generator project for your FIFOs

We first have to create a CORE Generator project that will contain our FIFOs.

  1. From the “Start” menu, open Xilinx CORE Generator.
  2. Select “File->New Project”.
  3. Click “Browse” and select an appropriate location for the Coregen project. Select the folder where you normally place your projects, for example “C:\ML505\Projects”, and create a sub-folder called “ClockCrossFIFO”. Open this folder and click “OK”.
  4. You will be asked for the specifications of the FPGA you are using. All the cores you generate under this CORE Generator project file will be customized for the FPGA you specify here. Under the “Part” tab, select these options: Family “Virtex5”, Device “xc5vlx50t”, Package “ff1136”, Speed grade “-1”. Click “OK”. Note: If you are not using the ML505 board, these specifications may not apply to you. You will have to enter the details corresponding to the specific FPGA that you are using.


    Under the “Generation” tab, you can specify how you want your IP cores to be generated. Be sure that “VHDL” output is selected as shown below.

     

  5. When you have created your CORE Generator project, click on the “View by Function” tab to get a list of cores that you are able to generate.

Generate the 16 bit to 32 bit FIFO Core

  1. Open “Memories & Storage Elements->FIFOs” and double-click on “FIFO Generator”.

     

  2. A dialog box should open to allow you to select the features of the FIFO you want. Re-name the FIFO as “fifo_16b_to_32b” and then enter the settings shown in the images below.






     

  3. Click “Finish”. Your FIFO will be generated and CORE Generator will display a list of all the generated files. Close this window.

Generate the 32 bit to 16 bit FIFO Core

  1. Open “Memories & Storage Elements->FIFOs” and double-click on “FIFO Generator”.

     

  2. A dialog box should open to allow you to select the features of the FIFO you want. Re-name the FIFO as “fifo_32b_to_16b” and then enter the settings shown in the images below.






     

  3. Click “Finish”. Your FIFO will be generated and CORE Generator will display a list of all the generated files. Close this window.

Examine the Generated Files

We will now examine the generated files and explain their purpose and utility. Open “Windows Explorer” and browse to the Coregen folder that we just created. We should see a list of files as shown below:

You should notice that there are two sets of files, one set for the 16 bit to 32 bit FIFO and one for the 32 bit to 16 bit FIFO. We will discuss the generated files for the first FIFO and you can assume that the files for the other FIFO are equivalent.

  • Netlist File (fifo_16b_to_32b.ngc)

    The NGC file (or blackbox file) is an implementation netlist file for the FIFO that we can directly include in our designs without requiring any VHDL code.

  • Wrapper File (fifo_16b_to_32b.vhd)

    VHDL wrapper for simulating the FIFO.

  • Instantiation Template File (fifo_16b_to_32b.vho)

    The instantiation template provides a template for declaring the FIFO component and instantiating it. You use this template by copying and pasting it to your design and making the necessary connections.

  • CORE Generator Input File (fifo_16b_to_32b.xco)

    Contains the parameters used to regenerate the core.

  • File List (fifo_16b_to_32b_flist.txt)

    A text file listing all the generated files for this core.

  • Readme File (fifo_16b_to_32b_readme.txt)

    A text file listing all the generated files and what they are used for.

  • ISE Project Navigator interface file (fifo_16b_to_32b_xmdf.tcl)

    ISE uses this file to determine how the FIFO core files can be integrated into an ISE project.

  • FIFO Generator User Guide (fifo_generator_ug175.pdf)

    The user guide explains how to generate the FIFO using CORE Generator and also how to use it.

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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