Recently I was asked this question by a reader: “Is it possible to make a design large enough to make the FPGA melt?”.
I don’t know why you would want to melt an FPGA, but the idea is interesting so its worth writing about. I’ve actually had people tell me rumors that if you made a design that utilized 90-100% of the resources in an FPGA that it would melt itself. Anyone who’s seen how hot FPGAs can get might think that’s feasible at first glance, but its not that simple.
Firstly, if you want to melt an FPGA, you should first understand what makes it heat up. Most of the heat generated by an FPGA is created when flip-flops transition from one-to-zero or zero-to-one. To maximize the heat generated, we need to maximize the number of flip-flops in the design and the frequency at which they transition. This can be done by chaining together a large number of flip-flops one after the other and feeding the chain with a toggling signal. The easy way to code this is with a for loop generate statement. Let me know in the comments if you want this code, and if enough people are interested, I’ll code it and post it.
The bad news is, most FPGAs are made with internal thermal switches that cut the power to the device when the temperature exceeds a certain level (typically 85 degrees). That temperature, if maintained for long periods is enough to cause damage to the device, but not to melt it. Secondly, you probably could come up with a design that uses close to 100% of the FPGA resources without actually melting or damaging it, because the amount of heat generated is not just proportional to the number of resources used, but also the toggle rate of your design. But even if you were to make a design that uses 100% of the resources, it would take hours and hours to build the bitstream, I challenge someone to give it a try.
Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.
Recently I was working on the challenge to heat up an FPGA by its own intern configuration. Best solution I could thin of was implementing many fast clocked elements. In fact I configured the combinatorial elements as inverters and the sequential elements as always on latches. The used Virtex5 can contain ~30.000 of this element pairs. as we activated them, the temperature was rising very fast. After a minute or so, the temperature was at 100°C (measured by the internal temp diode). We turned it off, to not damage the device. The security switch, that is turning off the device at a curtain temperature can be deactivated. So in consideration of all this experiences I would say it is possible to destroy the FPGA, I just don’t want to try :-P