I know I’ve gone through the Base System Builder many times before but I’m writing a few more advanced tutorials for version 14.7 and they all need a starting point. So in this post we will use the handy Base System Builder of the Xilinx Platform Studio (EDK) to put together a simple project for the ZC706 evaluation board.


You will need the following :

  • Xilinx ISE Design Suite 14.7

Create the Project

Follow these steps to create the project:

  1. Open XPS by selecting “Start->Xilinx Design Tools->ISE Design Suite 14.7->EDK->Xilinx Platform Studio”.
  2. From the welcome screen, select “Create new project using Base System Builder” and OK.
  3. You will be asked to specify which folder to place the project. Click “Browse” and create a new folder for the project. You also need to select an interconnect type, select AXI System and click “OK”.
  4. The next page asks for information on the hardware platform you are using. We will be using the ZC706 Evaluation Platform. Make the selections shown in the below image and click “Next”.
  5. Now we have to select the peripherals to go in the design. The peripherals will all be connected to the ARM processor in the Zynq SoC via AXI interconnect. At the time I wrote this tutorial, the only peripherals available allow us to use the PCI Express interface, the DIP switches, the pushbuttons and the LEDs. We will leave the default setting which is to include ALL the standard peripherals.
  6. Click “Finish”.

Now you should have a complete EDK project for the ZC706. An EDK project essentially forms the “hardware” of any FPGA design. In more concrete terms, it allows you to generate a bitstream which you can use to configure the programmable logic in the Zynq SoC, forming custom digital circuits around the ARM processor. The interface between the custom logic and the ARM processor is implemented by an AXI interconnect.

Build the bitstream

The project is now ready to build.

  1. To generate the bitstream of the project, click “Generate Bitstream”. This can take quite some time to complete (half an hour), depending on your machine.

When the bitstream has been generated, you should see the following message in the console window:

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.

What next?

The bitstream we just made is not very useful on its own, we still need to write code to run on the processor in order to test and use the peripherals. In general, code for the processor is developed in the Xilinx SDK which will be the topic of the next tutorial.

The project files for this tutorial are available on Github at the link below:



Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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