Yesterday I received the bare PCBs for the SERDES SFP FMC, my new product that enables 2 multi-gigabit transceivers on the ZedBoard or other LPC FMC carriers that don’t have internal MGTs.

In the last couple of weeks I’ve been working hard on a demo design in Vivado which you can find on Github here:

So far all timing passes at the board’s top speed of 3.125Gbps (or 2.5Gbps with DC balanced encoding).

Here are a couple photos of the boards:



I’ve got to say that it feels great to share my work like this. One of the downsides of client work is that I don’t own the IP and its almost always confidential so I can’t share too many details about what I’m doing on my blog. Now it’s my product, my IP, and I decide how much of it I can share!

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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