Half the fun of making cool stuff is sharing it with others. The photos I’m sharing in this post are of my new M.2 NGFF loopback module – it’s a M.2 form-factor module with a loopback on each of the 4 PCIe lanes, as well as some electronics to test other connections such as the 3.3V power supply and the 100MHz clock. It allows my assembler to test the FPGA Drive boards that come out of production. The other half of the test jig is of course the FPGA board, which I’ve designed to be driven by the PicoZed 7015 (I’ll share photos of this board in a later post).

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The challenge in designing an automated test for the FPGA Drive boards is that they supply a lot of connections to the SSD (which must be checked), but the only connection that the FPGA has with the SSD is via the 4 PCIe lanes (1). So any manufacturing faults that are detected by the M.2 loopback module must be communicated to the FPGA via the 4x PCIe lanes. If I had placed a Zynq on the M.2 module, it would have been easy to communicate any number of faults to the FPGA, but then the module would have cost a hell of a lot more. So my solution was to use a PCIe MUX/DEMUX whose outputs are connected in loopback. One of the outputs of the MUX/DEMUX is looped back with it’s polarity reversed, while the other is looped back with normal polarity. This way, I can use the SEL pin of the MUX/DEMUX to indicate a manufacturing defect to the FPGA. With 4 lanes, I can signal 4 different types of manufacturing errors. By also using the device’s shutdown pin, which removes the loopback, I can signal 4 more defects.

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In the production test, the PicoZed 7015 sends a PRBS signal at 5Gbps on each of the 4 PCIe lanes. If the M.2 loopback module does not detect any manufacturing defects, all 4 PCIe lanes are connected in loopback with normal polarity. Any signal integrity problems should be detected by the PicoZed in the form of bit errors in the received PRBS signal. If the M.2 module detects a problem with the power supply, the 100MHz clock, the LED, the PEDET connection, the reset signal or the DEVSLP connection, it will result in one of the lanes being polarity reversed, or being disconnected – both of which can be detected by the PicoZed. The M.2 loopback module also has power resistors which draw 2.5A of current and make sure that the power supply meets the M.2 standard requirements.

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As the loopback module was designed to be compliant to the PCI Express M.2 specification, it can be used to test any M.2 carrier. If you want more information on these modules, or you’d like to purchase one, please contact me.

Notes: (1) Actually, the FPGA also has the PERST (reset) connection to the SSD, but we can’t use this signal for testing because (a) it’s driven by the FPGA Drive board on the PCIe edge-connector version and (b) it’s an input to the FPGA Drive FMC version.

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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