# Using SVN with HDL designs

Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs.

HDL designs typically involve source files, netlist files and bitstreams. As in software design, the best way to use SVN is to commit source files only. That means, don’t commit netlist files or bitstream files. Our challenge is to ensure that someone who loads our sources from SVN to a clean slate (let’s call him Jack) will be able to re-generate the netlists and bitstream files without a problem.

To give you an example, a Xilinx IP core can contain all of these file types:

• .MPD file (Description of the IP core)
• .PAO file (List of source files used by the core)
• .UCF file (Constraints specific to the core)
• .BBD file (List of netlists used by the core)
• .NGC file(s) (Netlists used by the core)
• .VHD file(s) (VHDL source files)
• .V file(s) (Verilog source files)

In this example, all the files are necessary so we should commit them all except the netlist files. Obviously, Jack will need the netlist files, so we must also commit all the source files necessary to re-build the netlist file.

If the netlist file was originally built by Core Generator, for example, a FIFO, then you will need to commit the two files that are necessary to re-build the netlist with Coregen:

• .CGP file - The coregen project file which contains details about the target FPGA.
• .XCO file - The core description file (one for each netlist).

You can commit these files in a unique sub-folder of the IP core (let’s say ngc_src). Now, Jack will have all the sources for the IP core and all the sources needed to build the netlists of the IP core.

But there is still a problem: Jack doesn’t want to open Coregen, build the netlist and copy it to the right location for all of your IP cores. Unless you want to make it hard for Jack, you should automate the process of generating the netlists. This can be done through a TCL script file. By adding a TCL script file to your IP core, you can have the netlist generated when the core is synthesized (in EDK for example).

I’ll talk about using TCL scripts for this in the next post. For now, here is a list of the critical source files that you need to commit to SVN for the different types of projects in the Xilinx ISE Design Suite 13.1.

### Xilinx Platform Studio (XPS or EDK) Project Critical Sources

• \system.xmp file - The project file.
• \system.mhs file - The hardware description file.
• \data\system.ucf - The constraints file.
• \etc\bitgen.ut - The bit gen file.
• \etc\fast_runtime.opt - The XFLOW options file.
• \etc\xmd_microblaze_0.opt - Script to run XMD.

### ISE Project Critical Sources

The product of an ISE project can be a netlist, a bitstream or both. Either way, you obviously need to commit the source files (VHDL or Verilog) and for projects that produce bitstreams, you need to commit the constraints file (.ucf). That leaves the project file:

• \projectname.xise - The ISE project file.

### Core Generator IP core Critical Sources

The product of a Core generator project is typically a netlist (.NGC file). These are the source files you should commit to be able to re-generate a netlist file from coregen.

• \corename.cgp - The coregen project file contains details about the target FPGA.
• \corename.xco - The core description file.