AC701 Evaluation Board

For those of you who want to experiment with processorless Ethernet on FPGAs, I’ve just released a 4-port example design that supports these Xilinx FPGA development boards:

• Artix-7 AC701 Evaluation board
• Kintex-7 KC705 Evaluation board
• Kintex Ultrascale KCU105 Evaluation board
• Virtex-7 VC707 Evaluation board
• Virtex-7 VC709 Evaluation board
• Virtex UltraScale VCU108 Evaluation board
• Virtex UltraScale+ VCU118 Evaluation board

Here’s the Git repo for the project: Processorless Ethernet on FPGA

Why processorless?

Pure hardware designs can trump software where the need for low latency and/or high throughput is greater than the need for flexibility and complexity (eg. the support of complex protocols). There are lots of applications that rely on hardware based packet processing to achieve their superior performance. High frequency trading platforms are often fed market pricing over multicast UDP, so their profitability is directly linked to their ability to process UDP with the lowest possible latency. Network security devices that monitor traffic usually need to be as transparent as possible while also being able to detect threats and take action with the lowest possible delay. Whatever your reason for processing Ethernet frames in the FPGA fabric, make sure that you consider both sides of the coin:

One of my most common customer requests is to speed up execution of a software application using FPGA hardware acceleration. If the application runs on a PC or server, you can achieve impressive performance gains by using off-the-shelf FPGA development boards for PCI Express.

Here is a comparison of the available 7 Series FPGA boards for PCI Express applications:

• (*) Note: These HPC FMC connectors are only partially populated which means that they wont be able to support all standard FMCs.
• There are many more FPGA boards for PCIe on the market, but I chose to limit the comparison to those that are more strongly supported by Xilinx.

The reason these types of boards are so useful in the hardware acceleration space is because PCI Express is the highest bandwidth, lowest latency link that you can have between a PC’s CPU and an external FPGA. There’s no use shipping off work to an FPGA if the time it takes the data to get there and back is more than the time saved through improved processing efficiency.