XUPV2P

Hardware Details

The Xilinx University Program Virtex-II Pro (XUPV2P) Development System from Digilent is a development board for the Virtex-II Pro FPGA. It contains many useful hardware features including:

• Xilinx Virtex-II Pro XC2VP30 FPGA
• 10/100Mbps Ethernet PHY
• USB port
• Compact Flash card slot
• XSGA Video port
• Audio Codec
• SATA connectors (2 hosts, 1 target)
• PS/2 and RS-232 ports
• High and Low Speed expansion connectors

Virtex-II Pro FPGA Details

The XUPV2P is loaded with a Virtex-II Pro FPGA:

Overview

In this tutorial we will improve on the Timer peripheral developed in Create a Simple Timer Peripheral. The improvement is achieved by enabling the peripheral to generate an interrupt when the timer expires. The PowerPC then processes the interrupt through an interrupt handler function which gets called whenever the interrupt occurs. In this example, the interrupt handler function will switch the state of the LEDs and reset the timer.

Figure: The Timer peripheral

Overview In this tutorial we will create a peripheral containing the Aurora core to implement a high speed serial transceiver with a RocketIO MGT. It will be an improved version of the Aurora transceiver developed in the tutorial titled Create an Aurora Transceiver. The improvement is achieved by connecting the peripheral to the PLB rather than the OPB, which allows much faster data transfer by virtue of a wider bus and Direct Memory Access capability.

Below we describe various problems with the XUPV2P board and/or XPS software, and the solution or work-around.

No Vista Support for 9.1 or Older Presently, the EDK and ISE platforms versions 9.1 and older do not support Vista. You must upgrade to version 9.2 to operate under Vista.

The Onewire Problem

Conditions

I am using the Digilent XUPV2P board with Xilinx Platform Studio v8.2i. I connect to my XUPV2P board via USB (i.e. not JTAG).

Overview In this tutorial we will create a peripheral containing the Aurora core to implement a high speed serial transceiver with a RocketIO MGT. The peripheral can be used to connect two XUPV2P boards using the SATA connectors and transfer data between them at 1.5Gbps. To test the design using only one XUPV2P board, we will instantiate two Aurora peripherals, assign them to different RocketIO MGTs and place a SATA cable between them to create a loop-back connection. The PowerPC will transfer data between the two Aurora peripherals simply by reading and writing to the read and write FIFOs. To test the design, the test application will write data to the write FIFO of the first Aurora peripheral and read it back from the read FIFO of the second Aurora peripheral. The Aurora peripheral will also have outputs indicating the status of the link. These outputs will be connected to the LEDs on the XUPV2P board.

Overview

In this tutorial we will use a RocketIO MGT for possibly its simplest application, a programmable oscillator. This can be achieved by feeding the MGT with a repetitive data pattern (e.g. “10101010101010101010”). By changing the data pattern we can adjust the output frequency and duty cycle.

Figure: The Oscillator peripheral

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The diagram above illustrates the oscillator peripheral. In it we use 4 registers to store a 4 x 32 bit repeating pattern to be fed to the RocketIO primitive (GT_CUSTOM). Note that we could have used any number of registers to store the pattern. In our user_logic.vhd file we instantiate the GT_CUSTOM and create a counter which we use for loading the GT_CUSTOM. The counter counts from 1 to 4 and each time it loads the corresponding register contents into the GT_CUSTOM for transmission.

Here are links to some useful reference documents:

Xilinx
Xilinx University Program Virtex-II Pro Development System
Hardware Reference Manual

Xilinx
XUPV2P Schematics
Complete Schematics for the XUPV2P Development Board

Xilinx
Embedded System Tools Reference Manual
Embedded Development Kit EDK 8.1i

Xilinx
Xilinx Synthesis Technology (XST) User Guide
Describes XST Support for HDL

Xilinx
Xilinx RocketIO Transceiver User Guide
User Guide for the RocketIO Multi-gigabit Transceiver

Overview

This tutorial is similar to the previous one titled: Integrating a Blackbox into a Peripheral however in this case, instead of integrating an .ngc file into a peripheral, we integrate one or more VHDL files. Sometimes we have a VHDL design that we developed in ISE, or some other program, and we would like to bring it into the EDK as a peripheral. In this tutorial, we will create the same multiplier peripheral as was created in the previous tutorial.

Overview

In this project, we will add code to a peripheral template generated by the Peripheral Wizard to create a simple timer. The timer peripheral will be used by the PowerPC to make the LEDs flash with a fixed period.

Figure: The Timer peripheral

The timer will use two registers, one to store the delay period and the other for starting, stopping and checking if the timer has expired. We will call the first register the delay register and the second register the control register. The delay register will be set by the software application to determine how long of a delay it requires. This value will remain in the delay register unchanged and the software application will be able to read this value if for some reason it needs to. The control register will only use the first two bits, being bit 0 and bit 1. Bit 0 will be read-only and will be used by the timer peripheral to signal to the software application that the timer has expired. Bit 1 will be read and writeable, and it will be used by the software application to make the timer “run”. When a “1” is written to this bit, the timer will start counting down from the delay value. When a “0” is written to this bit, the timer will reset.

Overview

Sometimes we have an .ngc file from CORE Generator (or some other source) that we would like to bring into EDK as a peripheral. This project is a simple example of integrating a blackbox design into a peripheral generated by the Peripheral Wizard. We will first create a blackbox multiplier using the Xilinx CORE Generator and then we will use the generated .ngc file in our peripheral.

The multiplier will take in two 16 bit unsigned inputs and have a 32 bit unsigned output. A single 32 bit write to the peripheral will contain the two 16 bit inputs, separated by the lower and higher 16 bits. A single 32 bit read from the peripheral will contain the result from the multiplication of the two 16 bit inputs. Instead of registers, we will use a read and write FIFO for the interface with the software application. In this way, the peripheral write FIFO can be loaded with a number of multiplications to perform, and the results can be pushed into the read FIFO for the software application to retrieve at its convenience. Practically, this design does not serve much purpose, but it is a simple demonstration of integrating blackbox designs into peripherals.