Hard Processor

The PowerPC is a “hard” processor built into the Virtex II Pro FPGA. This is opposed to a “soft” processor that is implemented in a hardware description language (HDL) such as the Microblaze processor from Xilinx. The projects in this document focus on using the PowerPC with peripherals implemented in VHDL. The peripherals will be either provided by the Xilinx software or designed by the FPGA developer.

The Link to Peripherals: OPB and PLB

When designing projects that use the PowerPC, it is important to understand how the PowerPC interacts with peripherals. Within the Virtex-II Pro FPGA there are two buses for interfacing the PowerPC to the peripherals: the Processor Local Bus (PLB) and the On-chip Peripheral Bus (OPB). The PLB is a high-performance bus that directly connects the PowerPC to memory and high-performance peripherals. The OPB is used to connect slower peripherals. The PLB and OPB connect through a bridge. In this configuration, the slower peripherals on the OPB do not place a load on the high-speed PLB. The bus connections are illustrated in the diagram below.

Figure: Bus connections

Most of the projects on this website will use peripherals that connect to the OPB, however in some projects, the peripherals will directly connect to the PLB for extra speed.

Registers for Input and Output

Any peripheral core will have inputs and outputs that we would like to have accessible to the PowerPC. For example, for a “multiplier” peripheral, the inputs could be two sets of 32 bits to represent the numbers to multiply, and the output could be one set of 32 bits to represent the result. To make these inputs and outputs available to the PowerPC, we need to integrate registers into the peripheral to form the inputs and outputs. Then we need to integrate an OPB or PLB handler into the peripheral to provide read and write access to the registers. Effectively, the PowerPC will access the inputs and outputs of the peripheral by reading and writing from registers that it accesses via the OPB or PLB. The diagram below illustrates the PowerPC to peripheral communication through an OPB. Click on the image to view it with a higher resolution.

Figure: PowerPC to peripheral communication

In the standard peripherals provided by Xilinx, the OPB/PLB handler and registers are already incorporated into the peripheral. However, when designing our own peripherals, or when using cores that don’t have an OPB/PLB interface, we need to develop the registers and OPB/PLB handler ourselves. Fortunately, the Peripheral Wizard in the XPS software can help us in this task. The Peripheral Wizard can provide us with a template for the read and write registers, as well as the OPB or PLB handler which we can modify to our needs.

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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