Tutorial Overview

In this tutorial, we will generate an Aurora IP core using the Xilinx CORE Generator version 10.1. The Aurora core can be used as a high-speed serial communications link for connecting multiple FPGAs or interfacing to other serial devices.


To generate the Aurora core with CORE Generator, you will first need to register with Xilinx to obtain a license to use the Aurora core. It is a free and simple process that involves accepting a license agreement. To start your registration, follow this link:


Once you have successfully registered, you must follow the links to the Aurora downloads and then select “Request LogiCORE IP Aurora License File”. This takes you to the license key request form into which you will enter your email address to receive your license key. The license key will be sent to you by email as an attached .zip file. The email will contain instructions on installing the license key, which basically involves extracting the .zip file contents to your C drive. Once you have extracted the .zip file to your hard drive, you will be able to access the Aurora core in the CORE Generator.

You will also need to do the following:

  • Buy an ML505/ML506/ML507 or XUPV5 board if you don’t already have one. Xilinx supplies the ML50x boards, but the best deal is the XUPV5 from Digilent. Click the Digilent link for more information.

Generate the Aurora IP Core

After installing the license, follow these instructions for generating the Aurora IP core.

  1. From the “Start” menu, open Xilinx CORE Generator.
  2. Select “File->New Project”.
  3. Click “Browse” and select an appropriate location for the Coregen project. Select the folder where you normally place your projects, for example “C:\ML505\Projects”, and create a sub-folder called “AuroraCore”. Open this folder and click “OK”.
  4. You will be asked for the specifications of the FPGA you are using. All the cores you generate under this CORE Generator project file will be customized for the FPGA you specify here. Under the “Part” tab, select these options: Family “Virtex5”, Device “xc5vlx50t”, Package “ff1136”, Speed grade “-1”. Click “OK”. Note: If you are not using the ML505 board, these specifications may not apply to you. You will have to enter the details corresponding to the specific FPGA that you are using.

    Under the “Generation” tab, you can specify how you want your IP cores to be generated. Be sure that “VHDL” output is selected as shown below.


  5. When you have created your CORE Generator project, click on the “View by Function” tab to get a list of cores that you are able to generate.
  6. Open “Communication & Networking->Serial Interfaces” and double-click on “Virtex-5 Aurora”.


  7. A message box should open saying that you have the “Full license” to use the Aurora core. It may also say that the license does not give you access to the source code, but you can ignore this. Click “OK”.
  8. A dialog box should open to allow you to select the features of the Aurora Core you want. Enter the settings shown in the image below.


  9. Click “Finish”. Your Aurora core will be generated and CORE Generator will display a list of all the generated files. Close this window, and close CORE Generator.

Examine the Generated Files

We will now examine the generated files and explain their purpose and utility. Open “Windows Explorer” and browse to the Coregen folder that we just created. We should see a list of files as shown below:

We can see that CORE Generator has placed some files in the coregen project folder, and it has also created a folder specifically for the Aurora core called “aurora_201”. We will discuss the files that you will find most useful.

  • Instantiation Template File (aurora_201.vho)

    The instantiation template provides a template for declaring the Aurora component and instantiating it. If you are already familiar with the Aurora core, you could use this template by copying and pasting it to your design and making the necessary connections. If it is your first time using the Aurora core, you might prefer to use the examples provided in the “aurora_201” folder.

  • Virtex-5 FPGA Aurora v3.0 User Guide (ug353.pdf)

    The User Guide for the Aurora core provides a detailed description of the workings of the core and the protocol. Read this documentation to better understand how to use and interface to the Aurora core.


  • Aurora Core Datasheet (v5_aurora_v3_0.pdf)

    The Aurora core datasheet provides the technical specifications for the Aurora core such as the total resources that it occupies and a short description of its parameters.


  • Virtex-5 FPGA Aurora v3.0 Getting Started Guide (v5_aurora_v3_0_gsug352.pdf)

    The getting started guide is probably the most useful document for people new to the Aurora core. It provides an introduction to the Aurora core and gives a detailed description of the example that is generated with the core. It also contains instructions on how to simulate/implement the example.


  • Examples folder

    In the “examples” folder you will find the source code for the example described in the Getting Started Guide. The example can be implemented in ISE and it includes a frame generator and frame checker to test the Aurora core in a loopback connection.


  • Src folder

    The “src” folder contains the VHDL source for the Aurora core. You will most likely be able to use these files in your designs without having to modify them in any way.


  • Testbench folder

    The “testbench” folder contains a testbench for simulating the Aurora core example.


  • UCF folder

    The “ucf” folder contains two .ucf constraint files for use with the example design and with the Aurora core. You can use these .ucf files in your designs but you might want to change them to specify a different RocketIO GTP depending on your application.

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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