How to keep a signal name after mapping

Why can’t I find my signals in Chipscope inserter?

Often you want to assign a constraint to a particular signal in your design, or you want be able to find a particular signal in Chipscope inserter. In both cases, the signal must be in the physical design database (ie. in the .NCD file - Native Circuit Description) which is generated by the mapper. Not all signal names in your HDL code will end up in the NCD, some of them will be absorbed into logic blocks and grouped into a different signal name. To ensure that a particular signal name ends up in the NCD, it’s important to use the keep signal constraint.

When a design is mapped, some nets may be absorbed into logic blocks. The mapping tool does this because as a signal passes from one logic block to another, it can change name in your HDL code (eg. from data_in to data_out). As it is the same signal, the mapping tool gives it ONE name and it chooses among the names you have given it in your code.

When a net is absorbed into a block, it can no longer be seen in the physical design database. What this means in a practical sense is that you will no longer be able to refer to it in your UCF, and you will not find it in Chipscope inserter.

The “keep” constraint is a constraint that you put in your HDL code that prevents the signals you specify from being absorbed away.

In VHDL, before the begin statement, you must define keep as a string attribute and then assign the keep attributes as true for all the signals you want to keep.

attribute keep : string;
attribute keep of MyRefClk : signal is "true";
attribute keep of MyData   : signal is "true";

In Verilog, you would use the following lines:

// synthesis attribute keep MyRefClk "true";
// synthesis attribute keep MyData "true";

Both examples will keep the signal names MyRefClk and MyData in the physical design database and you will be able to refer to them in your UCF file and find them in Chipscope inserter.