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How to keep a signal name after mapping
Using the KEEP constraint in VHDL and Verilog to preserve signal names through synthesis
June 27, 20112 minutes
EDK Version 13.1 Navigation
A visual guide to navigating the Xilinx Platform Studio (XPS) version 13.1 interface
June 25, 20113 minutes
Don't forget SIGIS = CLK in your MPD files!
Why omitting SIGIS = CLK in your EDK MPD file causes clock-related debugging headaches
June 23, 20114 minutes
FPGA Mezzanine Card (FMC) is a game-changer
An introduction to the FMC standard and how it enables modular FPGA I/O design
June 23, 20113 minutes
Convert an ML505 EDK project for the XUPV5
How to retarget an ML505 EDK project to the XUPV5 by changing the FPGA and pin constraints
June 19, 20116 minutes
Creating a project using the Base System Builder
Step-by-step tutorial for creating an EDK project with the Base System Builder in version 13.1
June 19, 20115 minutes
Big changes are coming!
Announcing site updates including a move to WordPress, comments, and new tutorials for ISE 13.1
June 15, 20111 minute
Loading Designs from Compact Flash
Load FPGA designs automatically from compact flash on the ML505/XUPV5 board at power-on
October 12, 20092 minutes
Convert Bit Files to System ACE Files
Convert FPGA bit files to System ACE format for loading designs from compact flash
October 10, 20092 minutes
Use iMPACT to Download a Bit File
Download a bit file to your FPGA using iMPACT from the command line with a simple script
October 10, 20091 minute