I’ve been totally overloaded with projects in the last couple months but I’m back with some really exciting news today. A few months back a company called IntelliProp, based in Colorado, released a NVMe Host Accelerator IP core for interfacing FPGAs with NVMe SSDs. This IP core allows reads and writes to be performed directly from the FPGA fabric, without the latency overhead of an operating system (read about the NVMe speed tests I did under PetaLinux). IntelliProp has tested their IP core with an FPGA Drive FMC loaded with a Samsung 950 Pro 256GB SSD and here are the results:

These numbers are impressive, considering that test results on the same SSD by Arstechnica (probably using PCIe Gen3) showed write speeds of 944MBps and read speeds of 2,299MBps. IntelliProp’s IP is a great solution for applications needing large non-volatile storage and a high bandwidth channel to the FPGA fabric. One such application is high speed data acquisition, where you’ve got a lot of data coming in quickly and you need to store it for later processing, like what they’d use in the Large Hadron Collider. Another advantage of this solution is that SSDs typically store much more data per square inch than DDR memory, so some applications currently using DDR for the bulk of their data storage might have an reason to switch over to NVMe SSDs now that the simplicity and throughput of the interface has significantly improved.

For more information on IntelliProp’s NVMe Host Accelerator IP Core:

http://intelliprop.com/hardware-storage-design/ip-cores/nvme-host-accelerator-ip-core-IPC-NV164-HI.htm

For more information on the NVMe SSD to FPGA interface solution:

http://fpgadrive.com

In the next few days I’ll be trying to reproduce IntelliProp’s results on our own hardware and I’ll post the results soon after.

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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