This video demonstrates how you would typically go about accelerating a Python function or algorithm on the Zynq-7000 with PYNQ. The function I chose to base this video on is the Finite Impulse Response (FIR) filter because the SciPy package contains the lfilter function which can be used for this purpose, and because the Xilinx IP catalog has a free FIR filter IP core. If you instead wanted to implement the accelerator in HLS, the process would be very similar, you would just have to design your accelerator with AXI-Streaming interfaces and ensure that the TLAST signals were properly managed.

You can follow through the tutorial by copying and pasting the code from the Jupyter notebook below, or you can download the notebook and copy it to your PYNQ-Z1 board. I suggest that you generate the PYNQ overlay yourself by following the steps in the video, but I have also left a link to the files here.

The filter coefficients were generated using this free online FIR filter design calculator. I used a passband of 0-5MHz and a stopband of 10MHz to 50MHz. When you enter the coefficients into Vivado, the easiest way is to just copy them out of the Jupyter notebook below at the line “coeffs = [-255,-260,-312,…]” (only copy the numbers!).

Jeff is passionate about FPGAs, SoCs and high-performance computing, and has been writing the FPGA Developer blog since 2008. As the owner of Opsero, he leads a small team of FPGA all-stars providing start-ups and tech companies with FPGA design capability that they can call on when needed.

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