Creating a Base System for the Zynq in Vivado

Creating a Base System for the Zynq in Vivado

Tutorial Overview

In the ISE/EDK tools, we’d use the Base System Builder to generate a base project for a particular hardware platform. Now with Vivado, the process is a little different but we have more control in how things are setup and we still benefit from some powerful automation features. In this tutorial we’ll create a base design for the Zynq in Vivado and we’ll use the MicroZed board as the hardware platform.



Before following this tutorial, you’ll need the following:

  • Vivado 2014.2
  • MicroZed
  • Platform Cable USB II (or equivalent JTAG programmer)

Create a new Vivado project

Follow these steps to create a new project in Vivado:

  1. Open Vivado. From the welcome screen, click “Create New Project”.fpga_developer_20140731_090803
  2. Specify a folder for the project. I’ve created a folder named “microzed_custom_ip”. Click “Next”.fpga_developer_20140731_090921
  3. For the Project Type window, choose “RTL Project”. Click “Next”.fpga_developer_20140731_091123
  4. For the Add Sources window, click “Next”. We will add our multiplier source code later.
  5. For the Add Existing IP window, click “Next”.
  6. For the Add Constraints window, click “Next”.
  7. For the Default Part window, select the “MicroZed Board” and click “Next”.fpga_developer_20140731_091302
  8. Click “Finish” to complete the new project wizard.


Change the project’s default language

By default, the project will be created using Verilog as the default language. As we’ll be importing VHDL, let’s change that to VHDL:

  1. From the menu, select Tools->Options.
  2. In the “General” tab select target language : VHDL.


Setup the Zynq PS

The new Vivado project starts off blank, so to create a functional base design, we need to at least add the Zynq PS (processor system) and make the minimal required connections. Follow these steps to add the PS to the project:

  1. From the Vivado Flow Navigator, click “Create Block Design”.fpga_developer_20140731_092018
  2. Specify a name for the block design. Let’s go with the default “design_1” and leave it local to the project. Click “OK”.fpga_developer_20140731_092055
  3. In the Block Design Diagram, you will see a message that says “This design is empty. To get started, Add IP from the catalog.”. Follow this advice by clicking on the blue “Add IP” link, or by using the “Add IP” icon.fpga_developer_20140731_092511
  4. The IP catalog should appear. Go to the end of the list and double click on the block named “ZYNQ7 Processing System” – it should be the second last on the list. Vivado will now add the PS to the block diagram.fpga_developer_20140731_092548
  5. In the Block Design Diagram, you will see a message that says “Designer Assistance available. Run Block Automation”. Click on the “Run Block Automation” link and select “processing_system7_0” from the drop-down menu. Block Automation makes connections and pin assignments to external hardware such as the DDR and fixed IO. It does this using the board definition of the hardware platform you specified when you created the project (MicroZed). We could make these connections ourselves if we were using a custom board, but for off-the-shelf boards, Block Automation makes the process a lot easier.fpga_developer_20140731_092844
  6. In the Block Automation window, make sure “Apply Board Preset” is ticked and click “OK”.fpga_developer_20140731_092950
  7. Now our block diagram has changed and we can see that the DDR and FIXED_IO are connected externally. Now the only remaining connection to make is the clock that we will use for the AXI buses. We must configure the Zynq to generate a clock and enable a general purpose AXI bus. To make these settings, double click on the Zynq PS block.fpga_developer_20140731_094013
  8. The Re-customize IP window will open. From the Page Navigator, select “Clock Configuration” and open the “PL Fabric Clocks” tree.fpga_developer_20140731_094152
  9. Make sure that the FCLK_CLK0 is enabled (ticked) and that it is set for a frequency of 100MHz. This will be our AXI clock.
  10. Now from the Page Navigator, select “PS-PL Configuration” and open the “GP Master AXI Interface” tree.
  11. Tick the “M AXI GP0 interface” checkbox to enable it.fpga_developer_20140731_094501
  12. Now click “OK” to close the Re-customize IP window.
  13. You should now see a new input port on the left side of the Zynq PS block. This is the AXI clock input. fpga_developer_20140731_094556We must now connect the FCLK_CLK0 output to the AXI clock input. To do this, click on the FCLK_CLK0 output and then click on the M_AXI_GP0_ACLK input. This will trace a wire between the pins and make the connection.fpga_developer_20140731_094805

Create the HDL wrapper

Now the Zynq is setup and all we need to do to create a functional project is to create a HDL wrapper for the design.

  1. Open the “Sources” tab from the Block Design window.fpga_developer_20140731_095715
  2. Right-click on “design_1” and select “Create HDL wrapper” from the drop-down menu.fpga_developer_20140731_095854
  3. From the “Create HDL wrapper” window, select “Let Vivado manage wrapper and auto-update”. Click “OK”.fpga_developer_20140731_095925

From this point, we have a base design containing the Zynq PS from which we could generate a bitstream and test on the MicroZed. We haven’t exploited any of the FPGA fabric, but the Zynq PS is already connected to the Gigabit Ethernet PHY, the USB PHY, the SD card, the UART port and the GPIO, all thanks to the Block Automation feature. So there is already quite a lot we could do with the design at this point, such as running Linux on the PS or running a bare metal application on it.


Generate the bitstream

To generate the bitstream, click “Generate Bitstream” in the Flow Navigator.fpga_developer_20140731_102843

Once the bitstream is generated, the following window appears. Select “Open Implemented Design” and click “OK”.


The implemented design will open in Vivado showing you a map of the Zynq device and how the design has been placed. In our case, we haven’t used any of the FPGA fabric (only the PS), so the map is empty for the most part.


Export the hardware to SDK

Once the bitstream has been generated, the hardware design is done and we’re ready to develop the code to run on the processor. This part of the design process is done in Xilinx Software Development Kit (SDK), so from Vivado we must first export the project to SDK.

  1. In Vivado, from the File menu, select “Export->Export hardware”.fpga_developer_20140731_141646
  2. In the window that appears, tick “Include bitstream” and click “OK”.fpga_developer_20140731_141701
  3. Again from the File menu, select “Launch SDK”.fpga_developer_20140731_141342
  4. In the window that appears, use the following settings and click “OK”.fpga_developer_20140731_141357

At this point, the SDK loads and a hardware platform specification will be created for your design. You should be able to see the hardware specification in the Project Explorer of SDK as shown in the image below.


You are now ready to create a software application to run on the PS.


Create a Software application

At this point, your SDK window should look somewhat like this:


To demonstrate creating an application for the Zynq, we’ll create a hello world application that will send “hello world” out the UART and to our PC.

  1. From the File menu, select New->Application Project.fpga_developer_20140731_143442
  2. In the first page of the New Project wizard, choose a name for the application. I’ve chosen hello_world. Click “Next”.fpga_developer_20140731_143532
  3. On the templates page, select the “Hello World” template and click “Finish”.fpga_developer_20140731_143654
  4. The SDK will generate a new application which you should find in the Project Explorer as in the image below.fpga_developer_20140731_151916

The hello_world folder contains the software application, which you can browse and modify. I suggest you take a look at the code that is contained here and get familiar with it.

The hello_world_bsp folder contains the Board Support Package, which is a bunch of libraries that are provided for accessing the various peripherals and features of the Zynq. In general, it’s better not to modify this code because it gets written over every time you use the “Clean project” option. Instead, if you want to make customizations, try to keep it in the application folder.

Once the software application has been created, it is automatically built. Once the application is built, we are ready to test the design on hardware.

Test the design on the hardware

To test the design, we are using the MicroZed board from Avnet. Make the following setup before continuing:

  1. On the MicroZed, set the JP1, JP2 and JP3 jumpers all to the 1-2 position.fpga_developer_20140731_144826
  2. Connect the USB-UART (J2) to a USB port of your PC.
  3. Connect a Platform Cable USB II programmer (or similar device) to the JTAG connector. Connect the programmer to a USB port of your PC.setup


Now you need to open up a terminal program on your PC and set it up to receive the “hello world” message. I use Miniterm because I’m a Python fan, but you could use any other terminal program such as Putty. Use the following settings:

  • Comport - check your device manager to find out what comport the MicroZed popped up as. In my case, it was COM12 as shown below.fpga_developer_20140731_150007
  • Baud rate: 115200bps
  • Data: 8 bits
  • Parity: None
  • Stop bits: 1

Now that your PC is ready to receive the “hello world” message, we are ready to send our bitstream and software application to the hardware.

  1. In the SDK, from the menu, select Xilinx Tools->Program FPGA.fpga_developer_20140731_150413
  2. In the Program FPGA window, we select the hardware platform to program. We have only one hardware platform, so click “Program”.fpga_developer_20140731_150540
  3. The bitstream will be loaded onto the Zynq and we are ready to load the software application. Select the hello_world folder in the Project Explorer, then from the menu, select Run->Run.fpga_developer_20140731_150759
  4. In the Run As window, select “Launch on Hardware (GDB)” and click “OK”.fpga_developer_20140731_150845
  5. The application will be loaded on the Zynq PS and it will be executed. Look out for the “Hello World” message in your terminal window!


What now?

In the following tutorials I’ll go through more concepts such as:

  • Creating a custom IP block and integrating your own HDL code
  • Using the DMA engine for transferring data between IP and memory
  • Running Linux on the PS
  • Accessing IP through a Linux application

Source code

The TCL build script and source code for this project is shared on Github here:

For instructions on rebuilding the project from sources, read my post on version control for Vivado projects.

See also