Using the AXI DMA Engine

Update 2014-08-06: This tutorial is now available in a Vivado version - Using the AXI DMA in Vivado One of the essential devices for maximizing performance in FPGA designs is the DMA Engine. DMA stands for Direct Memory Access and a DMA engine allows you to transfer data from one part of your system to another. The simplest usage of a DMA would be to transfer data from one part of the memory to another, however a DMA engine can be used to transfer data from any data producer (eg. [Read More]

How to download and build my Github FPGA projects

A while back I started sharing FPGA projects and code on Github. As I typically only commit sources and not generated files, the process of rebuilding the projects from sources can be a little tricky if you’re not used to working with the Xilinx tools. In this post I’ll explain exactly how you can download and rebuild one of my projects, and hopefully it will make the projects useful to more people. [Read More]

Creating a project using the Base System Builder

I know I’ve gone through the Base System Builder many times before but I’m writing a few more advanced tutorials for version 14.7 and they all need a starting point. So in this post we will use the handy Base System Builder of the Xilinx Platform Studio (EDK) to put together a simple project for the ZC706 evaluation board. Requirements You will need the following : Xilinx ISE Design Suite 14. [Read More]

How to read an NGC netlist file

For the occasions that you find yourself with a netlist file and you don’t know where it came from or what version it is, etc. this post is about how you can interpret the netlist file (ie. convert it into something readable). Today I found myself with two netlists and I needed to know if they were the same. Yes of course you can try comparing the two files with a program such as Beyond Compare, but if the netlists were compiled on separate dates, you will have trouble recognizing this from the raw binary data. [Read More]

How to read an NCD file

Sometimes we end up with two versions of the same design, where one works and one doesn’t work. If the code is the same, typically the problem is in placement of your primitives. In this case we would like to compare the two designs at a to find out what exactly has changed in the placements. This is where reading the NCD file (the Native Circuit Description file) can be useful. [Read More]

Using SVN with HDL designs

Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs. HDL designs typically involve source files, netlist files and bitstreams. As in software design, the best way to use SVN is to commit source files only. [Read More]

Write a software application with SDK

In the previous tutorial titled Creating a project using Base System Builder, we used the Embedded Development Kit (EDK) to create a hardware design composed of IP cores and a Microblaze soft processor. In this tutorial, we will complete the design by writing a software application to run on the Microblaze processor. In version 13.1, this is done using the Software Development Kit (SDK) and it is no longer “doable” in the EDK. [Read More]

EDK Version 13.1 Navigation

The diagram below shows the EDK window with an open project. The important areas are labelled with numbers 1 to 6. 1. Project Information This area contains information about the project and contains two tabs: Project and IP Catalog. The Project tab lists the project files and also some of the project settings such as target FPGA. The IP catalog contains a list of the peripherals or IP cores that your project has access to. [Read More]

Don't forget SIGIS = CLK in your MPD files!

The other day I wasted hours trying to figure out why my peripheral wasn’t properly clocking Chipscope. Basically I had my peripheral generating a clock and data which I plugged directly into a Chipscope ILA peripheral. When I looked at the Chipscope data, it was sort of random but sort of looked right at the same time. I eventually realized that in my MPD file for the peripheral, I had forgotten to specify that my clock output was in fact a “clock” output by using the SIGIS = CLK parameter. [Read More]

Convert an ML505 EDK project for the XUPV5

For some reason, the Base System Builder in EDK doesn’t support the XUPV5 board so when making an EDK project for the XUPV5 we have to select the ML505 board and modify the project settings later. If you have not yet created an EDK project, you should read the previous post Creating a project using the Base System Builder, and then continue from these instructions. Change the target FPGA The ML505 is based on the Virtex-5 XC5VLX50T whereas the XUPV5 is based on the Virtex-5 XC5VLX110T, so the first thing we must do is change the target FPGA of the project. [Read More]