PetaLinux build artifacts

How to keep them and where to find them

PetaLinux build artifacts
These tips apply to PetaLinux 2020.2. To save disk space, the PetaLinux tools deletes all build artifacts at the end of the build process. If you want to keep them for debugging or to help you develop a patch, you can add the following line to the project-spec/meta-user/conf/petalinuxbsp.conf file: RM_WORK_EXCLUDE += "recipe" Where recipe must be substituted with a valid recipe name such as the following: Sources Recipe name Kernel linux-xlnx FSBL fsbl U-Boot u-boot-xlnx PMU firmware pmu-firmware Device tree device-tree If you want to preserve the build artifacts of more than one component, you can append the recipe names, separated by spaces, for example, to preserve the kernel sources and the FSBL: [Read More]

Tcl Automation Tips for Vivado and Xilinx SDK

Tcl Automation Tips for Vivado and Xilinx SDK
Tcl automation is one of the most powerful features integrated into the Vivado and Xilinx SDK tools and should be fully exploited to maximize your productivity as an FPGA developer. In this post I’ve put together a “cheat sheet” of some of the most useful commands and tricks that you can use to get more done through Tcl scripting. If you want more things added to the list, please let me know in the comments section at the end. [Read More]

Modifying a BSP in Xilinx SDK

If ever you need to modify the BSP code in your Xilinx SDK project, keep two things in mind: Remember to re-build your application after the BSP has finished re-building. If you don’t re-build the software application, the .elf file will still contain the old BSP code and you wont see any change. Just re-save one of your application source files to get SDK to re-build your application. NEVER do a “clean” on the BSP after having modified it because Xilinx SDK deletes the BSP and re-builds them from the repository sources located in C:\Xilinx\14. [Read More]

How to download and build my Github FPGA projects

A while back I started sharing FPGA projects and code on Github. As I typically only commit sources and not generated files, the process of rebuilding the projects from sources can be a little tricky if you’re not used to working with the Xilinx tools. In this post I’ll explain exactly how you can download and rebuild one of my projects, and hopefully it will make the projects useful to more people. [Read More]

How to read an NGC netlist file

For the occasions that you find yourself with a netlist file and you don’t know where it came from or what version it is, etc. this post is about how you can interpret the netlist file (ie. convert it into something readable). Today I found myself with two netlists and I needed to know if they were the same. Yes of course you can try comparing the two files with a program such as Beyond Compare, but if the netlists were compiled on separate dates, you will have trouble recognizing this from the raw binary data. [Read More]

How to read an NCD file

Sometimes we end up with two versions of the same design, where one works and one doesn’t work. If the code is the same, typically the problem is in placement of your primitives. In this case we would like to compare the two designs at a to find out what exactly has changed in the placements. This is where reading the NCD file (the Native Circuit Description file) can be useful. [Read More]

How to keep a signal name after mapping

Why can’t I find my signals in Chipscope inserter? Often you want to assign a constraint to a particular signal in your design, or you want be able to find a particular signal in Chipscope inserter. In both cases, the signal must be in the physical design database (ie. in the .NCD file - Native Circuit Description) which is generated by the mapper. Not all signal names in your HDL code will end up in the NCD, some of them will be absorbed into logic blocks and grouped into a different signal name. [Read More]

EDK Version 13.1 Navigation

The diagram below shows the EDK window with an open project. The important areas are labelled with numbers 1 to 6. 1. Project Information This area contains information about the project and contains two tabs: Project and IP Catalog. The Project tab lists the project files and also some of the project settings such as target FPGA. The IP catalog contains a list of the peripherals or IP cores that your project has access to. [Read More]

Don't forget SIGIS = CLK in your MPD files!

The other day I wasted hours trying to figure out why my peripheral wasn’t properly clocking Chipscope. Basically I had my peripheral generating a clock and data which I plugged directly into a Chipscope ILA peripheral. When I looked at the Chipscope data, it was sort of random but sort of looked right at the same time. I eventually realized that in my MPD file for the peripheral, I had forgotten to specify that my clock output was in fact a “clock” output by using the SIGIS = CLK parameter. [Read More]

Convert an ML505 EDK project for the XUPV5

For some reason, the Base System Builder in EDK doesn’t support the XUPV5 board so when making an EDK project for the XUPV5 we have to select the ML505 board and modify the project settings later. If you have not yet created an EDK project, you should read the previous post Creating a project using the Base System Builder, and then continue from these instructions. Change the target FPGA The ML505 is based on the Virtex-5 XC5VLX50T whereas the XUPV5 is based on the Virtex-5 XC5VLX110T, so the first thing we must do is change the target FPGA of the project. [Read More]