Version control for Vivado projects

Version control for Vivado projects
Vivado generates a whole bunch of files when you create a project, and it’s not very clear on which are source files and which are generated files. The best approach is to consider them all to be generated files and to put none of them in version control. Instead, create a folder stucture for your sources that makes sense to you and use Tcl scripts to build the project and import the sources. [Read More]

How to download and build my Github FPGA projects

A while back I started sharing FPGA projects and code on Github. As I typically only commit sources and not generated files, the process of rebuilding the projects from sources can be a little tricky if you’re not used to working with the Xilinx tools. In this post I’ll explain exactly how you can download and rebuild one of my projects, and hopefully it will make the projects useful to more people. [Read More]

Using a TCL script to automatically generate netlists of an IP core

In a previous post I wrote about using SVN with HDL designs and how to do it most effectively. Here I want to write about having your peripheral cores automatically generate the netlists they use when the project is compiled, for example when you build the bitstream of an XPS project. Firstly I’ll give you an example where it would be useful. Let’s say I have a peripheral that contains a FIFO. [Read More]

Using SVN with HDL designs

Most companies involved in code design manage their sources using SVN. If you’re not doing it, you should be. There are a multitude of websites explaining the benefits of using SVN so I wont go there. This post is about the best way to use SVN for HDL designs. HDL designs typically involve source files, netlist files and bitstreams. As in software design, the best way to use SVN is to commit source files only. [Read More]