Quick look at Ethernet FMC Max

Opsero's new gigabit Ethernet FMC with SGMII

Quick look at Ethernet FMC Max

 Posted on October 9, 2024  |  Jeff Johnson

Ten years ago, almost to the day, I launched the Opsero Ethernet FMC. To my delight and surprise, many of our customers are still buying them today. Gigabit Ethernet still finds many uses in FPGA designs today, because it is simple to setup, the cabling is easy to buy and install, the throughput is ample for many applications and it is extremely versatile. This year, I felt that it was time to upgrade our Ethernet FMC offering, so we’ve launched two new products: Quad SFP28 FMC which I have introduced to you in earlier posts (here and here), and Ethernet FMC Max, which I would like to introduce to you in this post. [Read More]

Multi-port 25G Ethernet on Versal ACAP

A reference design that you can build and test

Multi-port 25G Ethernet on Versal ACAP

 Posted on October 8, 2024  |  Jeff Johnson

In this post we’re going to build and run our new multi-port 25G Ethernet reference design for Versal boards and the Opsero Quad SFP28 FMC. The design is based on the AMD Xilinx 10G/25G Ethernet Subsystem IP. Specifically, we’re going to boot PetaLinux on the VEK280 and establish a 25G Ethernet connection between it and a 25G network adapter that is installed in a Ubuntu PC. We’re doing this on Versal board VEK280 which is one of the few AMD FPGA-containing devices that can support 25G Ethernet at the time of writing. [Read More]

Introducing the Quad SFP28 FMC

High-speed Ethernet connectivity for FPGAs

Introducing the Quad SFP28 FMC

 Posted on July 16, 2024  |  Jeff Johnson

In the next few days I will kick off the launch of another new Opsero FMC product: the Quad SFP28 FMC. This FMC card has 4x SFP28 slots that are compatible with SFP, SFP+ and SFP28 modules. The FMC and the reference designs that we are currently developing will enable 4x 10G/25G Ethernet links on a multitude of FPGA/MPSoC/RFSoC development boards including the newer Versal ACAP boards. We’ve already pushed working 10G/25G designs to the Github repo for the ZCU104, ZCU102, ZCU106, ZCU111 and ZCU208 with more coming soon. [Read More]

The M.2 M-key Stack FMC Unveiled

A fresh approach to getting more from FMC

The M.2 M-key Stack FMC Unveiled

 Posted on April 3, 2024  |  Jeff Johnson

The FPGA Mezzanine Card standard (VITA 57.1) has significantly enhanced the FPGA ecosystem by decoupling the FPGA board from the input/output components. Years ago, if you wanted to process samples from an ADC, you would buy an FPGA board with an on-board ADC. If you wanted to add a DAC, or upgrade the ADC, you would replace the entire board! The FMC innovation provided developers with choice, so that they could select the right FPGA for their specific I/O requirements. [Read More]

Processorless Ethernet: Part 3

State machine based Ethernet on FPGA

Processorless Ethernet: Part 3

 Posted on May 1, 2021  |  Jeff Johnson

For those of you who want to experiment with processorless Ethernet on FPGAs, I’ve just released a 4-port example design that supports these Xilinx FPGA development boards: Artix-7 AC701 Evaluation board Kintex-7 KC705 Evaluation board Kintex Ultrascale KCU105 Evaluation board Virtex-7 VC707 Evaluation board Virtex-7 VC709 Evaluation board Virtex UltraScale VCU108 Evaluation board Virtex UltraScale+ VCU118 Evaluation board Here’s the Git repo for the project: Processorless Ethernet on FPGA [Read More]

Processorless Ethernet: Part 2

Modularizing the TEMAC example design

Processorless Ethernet: Part 2

 Posted on April 20, 2021  |  Pablo Trujillo

This article was written by Pablo Trujillo, an FPGA developer and consultant based in Valencia, Spain; a place that I happen to be very fond of, because of the many tapas bars and good eating/drinking to be done there. Pablo writes his own blog on FPGAs called Control Paths and he’s also a very active contributor to Hackster.io. In this article, Pablo explains how he has helped me to modularize the TEMAC example design that we looked at in an earlier post. [Read More]

Driving Ethernet ports without a processor

How to do it on an FPGA and why

Driving Ethernet ports without a processor

 Posted on February 16, 2021  |  Jeff Johnson

Gigabit Ethernet can be a very useful medium for transferring data very quickly from one point to another. It’s low-cost, high-bandwidth, well established technology and the cabling is easily obtained and installed. In embedded applications however, the throughput of Ethernet links is often held back by one thing: the processor. When using an FPGA, we can relieve the processor significantly by offloading work to the FPGA fabric, but often the only way to exploit the full potential of a Gigabit Ethernet link is to do away with the processor altogether. [Read More]

Measuring the maximum throughput of Gigabit Ethernet on the Ultra96

 Posted on July 17, 2019  |  Jeff Johnson

In this video I use Iperf to measure the actual maximum throughput of a Gigabit Ethernet port on the Ultra96 v2 running PetaLinux. The result that I get is pretty impressive: 910-940Mbps! To do this test yourself you’ll need to build the example design that you’ll find on our Github repo, and then prepare the SD card. Plug your SD card into your Ultra96 and fit the 96B Quad Ethernet Mezzanine on top of the Ultra96. [Read More]
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