For those of you who want to experiment with processorless Ethernet on FPGAs, I’ve just released a 4-port example design that supports these Xilinx FPGA development boards:
Artix-7 AC701 Evaluation board Kintex-7 KC705 Evaluation board Kintex Ultrascale KCU105 Evaluation board Virtex-7 VC707 Evaluation board Virtex-7 VC709 Evaluation board Virtex UltraScale VCU108 Evaluation board Virtex UltraScale+ VCU118 Evaluation board Here’s the Git repo for the project: Processorless Ethernet on FPGA
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This article was written by Pablo Trujillo, an FPGA developer and consultant based in Valencia, Spain; a place that I happen to be very fond of, because of the many tapas bars and good eating/drinking to be done there. Pablo writes his own blog on FPGAs called Control Paths and he’s also a very active contributor to Hackster.io. In this article, Pablo explains how he has helped me to modularize the TEMAC example design that we looked at in an earlier post.
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Gigabit Ethernet can be a very useful medium for transferring data very quickly from one point to another. It’s low-cost, high-bandwidth, well established technology and the cabling is easily obtained and installed. In embedded applications however, the throughput of Ethernet links is often held back by one thing: the processor. When using an FPGA, we can relieve the processor significantly by offloading work to the FPGA fabric, but often the only way to exploit the full potential of a Gigabit Ethernet link is to do away with the processor altogether.
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Most FPGA/SoC dev boards have a flash device for non-volatile storage. Typically it would be either a Quad SPI flash (serial interface) or a Linear BPI flash (parallel interface). Although it can be used for storing anything, it’s typically used for storing the configuration for the FPGA or SoC (eg. the bitstream, FSBL, U-Boot, Linux Kernel). If the boot mode of the FPGA or SoC is appropriately set, on power-up it should read from the flash, load the bitstream into the FPGA and then load and run the software components.
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In this tutorial video, I bring-up the 3x Gigabit Ethernet ports on the MYD-Y7Z010 Development board from MYIR. Firstly, I create a Vivado design for this board, then I export it into the SDK and generate the echo server application for each of the 3 ports (note that the echo server application only supports one port at a time). At the end of the video, I test each of these designs on hardware and ensure that the ports are given an IP address via DHCP and that I can ping the port.
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This video demonstrates how you would typically go about accelerating a Python function or algorithm on the Zynq-7000 with PYNQ. The function I chose to base this video on is the Finite Impulse Response (FIR) filter because the SciPy package contains the lfilter function which can be used for this purpose, and because the Xilinx IP catalog has a free FIR filter IP core. If you instead wanted to implement the accelerator in HLS, the process would be very similar, you would just have to design your accelerator with AXI-Streaming interfaces and ensure that the TLAST signals were properly managed.
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In this video tutorial we create a custom PYNQ overlay for the PYNQ-Z1 board. Probably the simplest PYNQ overlay possible, it contains one custom IP (an adder) with an AXI-Lite interface and three registers accessible over that interface: a, b and c. To use the IP we write a number to input registers a and b, and then we read the output register c which contains the sum of a and b.
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Here’s a base project for the Arty board based on the Artix-7 FPGA. The Arty is a nice little dev board because it’s low cost ($99 USD) but it’s still got enough power and connectivity to make it very useful. I really like the fact that the JTAG and UART are both accessed through the same USB connector, so I only need to connect one USB cable.
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The AXI-Streaming interface is important for designs that need to process a stream of data, such as samples coming from an ADC, or images coming from a camera. In this tutorial, we go through the steps to create a custom IP in Vivado with both a slave and master AXI-Streaming interface. The custom IP will be written in Verilog and it will simply buffer the incoming data at the slave interface and make it available at the master interface - in other words, it will be a FIFO.
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In this video I create a simple Vivado design for the MYIR Z-turn Zynq SoM and we run a hello world application on it, followed by the lwIP echo server. We connect the Z-turn to a network, then we use “ping” and “telnet” to test the echo server from a PC that is connected to the same network.
If you want to try it out yourself, download the SD card boot files here:
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