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FPGA Developer
A tech blog on FPGA design by Jeff Johnson
How to accelerate a Python function with PYNQ
Accelerating a Python FIR filter on the PYNQ-Z1 by offloading computation to FPGA fabric
March 22, 20182 minutes
Avnet Silica's industrial networking demo features Ethernet FMC
Avnet Silica demos TSN and industrial networking on the Ethernet FMC at Embedded World 2018
March 17, 20181 minute
Create a custom PYNQ overlay for PYNQ-Z1
Tutorial on creating a simple custom PYNQ overlay with an HLS adder IP and testing it via Jupyter
March 15, 20182 minutes
Python for the Zynq and the PYNQ-Z1
Introduction to the PYNQ-Z1 board and using Python with Jupyter to program the Zynq SoC
February 27, 20183 minutes
IntelliProp Demos NVMe Host Accelerator on FPGA Drive
IntelliProp demonstrates 3200 MB/s read speeds with their NVMe IP on an Intel Arria 10 and FPGA Drive
February 26, 20181 minute
PetaLinux for Artix-7 Arty Base Project
Building and booting a PetaLinux project on the Arty A7 board with network connectivity
November 15, 20175 minutes
Artix-7 Arty Base Project
Building a base Vivado design for the Arty A7 board with hello world and lwIP echo server in SDK
November 8, 20173 minutes
Creating a custom AXI-Streaming IP in Vivado
Step-by-step tutorial for building a custom AXI-Streaming FIFO IP in Vivado and testing it with DMA
November 1, 20177 minutes
Quick look at the UltraZed-EG SoM
Overview of the UltraZed-EG System-on-Module and Zynq UltraScale+ MPSoC features
October 24, 20171 minute
Getting Started with the MYIR Z-turn
Creating a Vivado design for the MYIR Z-turn Zynq SoM and running hello world and lwIP echo server
October 18, 20173 minutes