While getting into the Kria KV260 Vision AI Starter Kit Applications I’ve had to install Vitis and PetaLinux 2022.1 on Ubuntu 20.04. In this post I just want to write out some clear instructions to make it a smoother process for others that need to do the same thing.
Step 1: Install dependencies It’s probably best to start by installing all of the dependencies of Vitis and PetaLinux 2022.1. Just open a terminal in Ubuntu by pressing Ctrl + Alt + T and run the following commands.
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Most FPGA/SoC dev boards have a flash device for non-volatile storage. Typically it would be either a Quad SPI flash (serial interface) or a Linear BPI flash (parallel interface). Although it can be used for storing anything, it’s typically used for storing the configuration for the FPGA or SoC (eg. the bitstream, FSBL, U-Boot, Linux Kernel). If the boot mode of the FPGA or SoC is appropriately set, on power-up it should read from the flash, load the bitstream into the FPGA and then load and run the software components.
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In this post we’re going to install PetaLinux 2020.1 from scratch on a virtual machine running Ubuntu 18.04.4 64-bit. The workstation on which I will be doing this has an Intel Xeon, 64GB RAM and 3TB HDD running Windows 10 64-bit. I’m assuming that your host machine is also running Windows.
Why run PetaLinux on a virtual machine? Here are the main advantages to using PetaLinux on a virtual machine:
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This is my guide for installing PetaLinux 2019.1 from scratch on a virtual machine. The VM will run Ubuntu 18.04.4 64-bit and the host workstation is an Intel Xeon with 64GB RAM and 3TB HDD running Windows 10 64-bit. The PetaLinux user guide says that the latest supported version of Ubuntu is 18.04.1 however in my experience it works just fine in the more recent 18.04.4 version.
Step 1: Create the Virtual Machine Get VirtualBox from here, then install and launch it.
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The AXI-Streaming interface is important for designs that need to process a stream of data, such as samples coming from an ADC, or images coming from a camera. In this tutorial, we go through the steps to create a custom IP in Vivado with both a slave and master AXI-Streaming interface. The custom IP will be written in Verilog and it will simply buffer the incoming data at the slave interface and make it available at the master interface - in other words, it will be a FIFO.
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Update 2017-11-01: Here’s a newer tutorial on creating a custom IP with AXI-Streaming interfaces
Tutorial Overview In this tutorial we’ll create a custom AXI IP block in Vivado and modify its functionality by integrating custom VHDL code. We’ll be using the Zynq SoC and the MicroZed as a hardware platform. For simplicity, our custom IP will be a multiplier which our processor will be able to access through register reads and writes over an AXI bus.
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In the previous tutorial on using the SDK, we exported our base project from EDK to SDK and then we ran a simple software application that printed “Hello World” in the terminal window. In this tutorial, we will do something more useful than saying hello, instead we will illustrate the concept of communicating with a peripheral from C code running on the Microblaze. More specifically, we will read the DIP switch settings and display them on the terminal screen using printfs.
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In the previous tutorial titled Creating a project using Base System Builder, we used the Embedded Development Kit (EDK) to create a hardware design composed of IP cores and a Microblaze soft processor. In this tutorial, we will complete the design by writing a software application to run on the Microblaze processor. In version 13.1, this is done using the Software Development Kit (SDK) and it is no longer “doable” in the EDK.
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Instructions
If you want to download a bit file (.bit) to your FPGA without using ISE or EDK, you can use iMPACT directly from the command line.
To start, you should copy your bit file to a known folder (eg. “C:MyFolder”) and rename it to download.bit if it isn’t already called that.
Then you should create an iMPACT script file called download.cmd. The script file is just a text file that you can create with Wordpad and it must contain the following text:
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Tutorial Overview
In this example, we will develop a driver for the 16x2 character LCD on the ML505/6/7 board. The LCD driver will be mostly a Microblaze design, as opposed to being an IP design. The physical interface to the LCD will be made through a GPIO peripheral. The signal timing requirements of the LCD will be achieved by using a Timer peripheral. The functions contained in the software application will control what is shown on the LCD.
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