Welcome to FPGA Developer
A publication about electronics and FPGAs by Jeff Johnson, consultant and designer of custom FPGA boards and solutions.
One question I get a lot about the Ethernet FMC is: What is the maximum throughput? It’s a good question, so I created an example design to help me get the answer. The maximum throughput test design, that you can download on Github, uses four hardware packet generators (coded in VHDL) to feed the Ethernet MACs with back-to-back packets. These packets then get sent out of the Ethernet ports and get looped back into another Ethernet port through a CAT-5 cable. Here is the block diagram:
I hooked up port 0 to loopback to port 2, and port 1 to loopback to port 3. I setup ports 0 and 1, and ports 2 and 3 to operate on separate (asynchronous) clocks – this way I could be sure that the adjacent lanes were asynchronous to each other, and thus be better positioned to catch crosstalk induced errors on the RGMII traces on the Ethernet FMC.
The results: 97% channel efficiency and an impressive 974Mbps effective throughput per channel. No crosstalk-induced errors. Very happy indeed.
Checkout the results here: Ethernet FMC performance benchmarks