Welcome to FPGA Developer

A publication about electronics and FPGAs by Jeff Johnson, consultant and designer of custom FPGA boards and solutions.

Introducing the Quad Gigabit Ethernet FMC

Introducing the Quad Gigabit Ethernet FMC

Here’s the next product in Opsero’s growing lineup of FPGA I/O cards: the Quad Gigabit Ethernet FMC. This low-pin-count FMC is loaded with four Marvell Gigabit Ethernet PHYs and enables FPGA networking applications on the ZedBoard and other LPC carriers. A demo design for the ZedBoard is available on Github at the link below and further demos will become available in the next few weeks:

https://github.com/fpgadeveloper/zedboard-qgige

Look out for more details including the technical specs, schematics and more on the soon to be launched product page.

 

quad-gige-1 quad-gige-2

If you want more information about the Quad Gigabit Ethernet FMC, or if you are interested in purchasing the board, please don’t hesitate to contact me.

Jeff holds a bachelors degree in Electrical Engineering from the University of Sydney, and has more than a decade of experience in electronic and FPGA design. He has worked for design houses in Australia and Canada developing electronic products for a wide range of industries and markets. Jeff now works as an electronic design consultant and offers electronic and FPGA design services through his company Opsero.

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Recent posts

Introducing the Quad Gigabit Ethernet FMC

Introducing the Quad Gigabit Ethernet FMC

Here’s the next product in Opsero’s growing lineup of FPGA I/O cards: the Quad Gigabit Ethernet FMC. This low-pin-count FMC is loaded with four Marvell Gigabit Ethernet PHYs and enables FPGA networking applications on the ZedBoard and other LPC carriers. A...
SERDES FMC first units

SERDES FMC first units

Here’s a peek at the first units of the SERDES FMCs, the first low pin-count FPGA Mezzanine Card to enable multi-gigabit transceivers on the ZedBoard and other FPGA boards that don’t have internal MGTs. The first board is designed for SFP modules for...
PCBs for the SERDES FMC

PCBs for the SERDES FMC

Yesterday I received the bare PCBs for the SERDES SFP FMC, my new product that enables 2 multi-gigabit transceivers on the ZedBoard or other LPC FMC carriers that don’t have internal MGTs. In the last couple of weeks I’ve been working hard on a demo design...
A first look at a first product

A first look at a first product

After years designing products for other companies, I’ve finally designed something for my own company. If you have a ZedBoard and you want to experiment with MGTs, now you can with my two new SERDES low-pin-count FMCs. Both boards use the DS32EL0421/DS32EL0124...
Using the AXI DMA in Vivado

Using the AXI DMA in Vivado

In a previous tutorial I went through how to use the AXI DMA Engine in EDK, now I’ll show you how to use the AXI DMA in Vivado. We’ll create the hardware design in Vivado, then write a software application in the Xilinx SDK and test it on the MicroZed board (source...
Creating a custom IP block in Vivado

Creating a custom IP block in Vivado

Tutorial Overview In this tutorial we’ll create a custom AXI IP block in Vivado and modify its functionality by integrating custom VHDL code. We’ll be using the Zynq SoC and the MicroZed as a hardware platform. For simplicity, our custom IP will be a multiplier which...
Version control for Vivado projects

Version control for Vivado projects

Vivado generates a whole bunch of files when you create a project, and it’s not very clear on which are source files and which are generated files. The best approach is to consider them all to be generated files and to put none of them in version control. Instead,...
Creating a Base System for the Zynq in Vivado

Creating a Base System for the Zynq in Vivado

Tutorial Overview In the ISE/EDK tools, we’d use the Base System Builder to generate a base project for a particular hardware platform. Now with Vivado, the process is a little different but we have more control in how things are setup and we still benefit from some...

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