A tech blog on FPGA design by Jeff Johnson, maker of the Ethernet FMC and FPGA Drive.

KickStarter Campaign Launched: OnCourse Goggles

In recent weeks I've been working with some great people on an incredible new product for open water swimmers: OnCourse Goggles. Today we announced the launch of a KickStarter campaign which might help us to reach more people with this...

Ethernet gets robust

Announcing that the Robust Ethernet FMC is now in stock and available for purchase. Checkout the flashy new images of the first units, ravaging Ethernet packets in this tough new form factor....

Back in black

Here's a look at a batch of Ethernet FMCs fresh off the production line.

Using Chipscope and SDK at the same time

Today I was having problems debugging a design in Chipscope and SDK. For some reason, every time I used the Chipscope trigger (either the armed trigger or immediate) the Microblaze would reset or jump to another part of the code. I figured that Chipscope was messing...

Sneak look at the new Robust Ethernet FMC

Here are the first images of my new product: the Robust Ethernet FMC. This new variation of the Ethernet FMC contains all the features of the standard version but has been designed to fit the 10mm height profile of the Vita 57.1 standard. The Robust Ethernet FMC is...

Comparison of Zynq SoMs

In the last year or so, there has been an explosion in the availability of System-on-Modules (SoMs) featuring the popular FPGA+ARM combo Zynq-7000 SoC from Xilinx. I've always promoted the idea that FPGAs and SoCs allow for faster design cycles and rapid...

1.8V Version Ethernet FMC now available

I recently received and tested the first 1.8V Ethernet FMCs and they are now available to buy on ethernetfmc.com. There are two main reasons why you'd actually want a 1.8V version: Firstly, some carriers only support VADJ of 1.8V (such as the VC707 and VC709)....

Ethernet FMC performance benchmarks released

One question I get a lot about the Ethernet FMC is: What is the maximum throughput? It's a good question, so I created an example design to help me get the answer. The maximum throughput test design, that you can download on Github, uses four hardware packet...

Ethernet FMC supports Xilinx Dev Boards

Support for the Xilinx Series-7 development boards AC701, KC705, VC707, ZC702 and ZC706 has been added to the Ethernet FMC product page. Now you can use the Ethernet FMC on any one of these boards and support up to 8 x gigabit Ethernet ports! That's right, the KC705,...

Ethernet FMC first units shipped

Today I'm excited to announce that the first Ethernet FMCs were shipped! I would like to say thanks to all those who pre-ordered the Ethernet FMC, thanks for your patience and confidence and I hope the product enables you to develop new and exciting technologies in...

Ethernet FMC is now available

Announcing that the new Ethernet FMC, a Quad Gigabit Ethernet FPGA Mezzanine Card (FMC) is now available to buy. The board is designed for easy integration with the ZedBoard, with open-source example designs so you can start designing your product sooner. The...

Introducing the Quad Gigabit Ethernet FMC

Here's the next product in Opsero's growing lineup of FPGA I/O cards: the Quad Gigabit Ethernet FMC. This low-pin-count FMC is loaded with four Marvell Gigabit Ethernet PHYs and enables FPGA networking applications on the ZedBoard and other LPC carriers. A demo design...

SERDES FMC first units

Here's a peek at the first units of the SERDES FMCs, the first low pin-count FPGA Mezzanine Card to enable multi-gigabit transceivers on the ZedBoard and other FPGA boards that don't have internal MGTs. The first board is designed for SFP modules for Ethernet and...

PCBs for the SERDES FMC

Yesterday I received the bare PCBs for the SERDES SFP FMC, my new product that enables 2 multi-gigabit transceivers on the ZedBoard or other LPC FMC carriers that don't have internal MGTs. In the last couple of weeks I've been working hard on a demo design in Vivado...

A first look at a first product

After years designing products for other companies, I've finally designed something for my own company. If you have a ZedBoard and you want to experiment with MGTs, now you can with my two new SERDES low-pin-count FMCs. Both boards use the DS32EL0421/DS32EL0124...

Using the AXI DMA in Vivado

In a previous tutorial I went through how to use the AXI DMA Engine in EDK, now I’ll show you how to use the AXI DMA in Vivado. We’ll create the hardware design in Vivado, then write a software application in the Xilinx SDK and test it on the MicroZed board (source...

Creating a custom IP block in Vivado

Tutorial Overview In this tutorial we’ll create a custom AXI IP block in Vivado and modify its functionality by integrating custom VHDL code. We’ll be using the Zynq SoC and the MicroZed as a hardware platform. For simplicity, our custom IP will be a multiplier which...

Version control for Vivado projects

Vivado generates a whole bunch of files when you create a project, and it’s not very clear on which are source files and which are generated files. The best approach is to consider them all to be generated files and to put none of them in version control. Instead,...

Creating a Base System for the Zynq in Vivado

Tutorial Overview In the ISE/EDK tools, we’d use the Base System Builder to generate a base project for a particular hardware platform. Now with Vivado, the process is a little different but we have more control in how things are setup and we still benefit from some...

Zynq and the trend towards ARM-FPGA architectures

Since the release of the Series 7 devices from Xilinx in 2011, one member of the family is clearly dominating the others in terms of popularity: the Zynq-7000 SoC. Did Xilinx put all their marketing efforts into the Zynq or is this proof of a new trend in FPGA...

Modifying a BSP in Xilinx SDK

If ever you need to modify the BSP code in your Xilinx SDK project, keep two things in mind: Remember to re-build your application after the BSP has finished re-building. If you don't re-build the software application, the .elf file will still contain the old BSP code...

Zynq-7000 HPBI Controller

Over the last few months I've been very busy thanks to the popularity of Xilinx's Zynq SoC. Here's the latest project I've been working on for Evans Analytical Group, a Zynq based controller for high-power burn-in of ASICs. This custom board uses the Zynq XC7Z020...

Comparison of 7 Series FPGA boards for PCIe

One of my most common customer requests is to speed up execution of a software application using FPGA hardware acceleration. If the application runs on a PC or server, you can achieve impressive performance gains by using off-the-shelf FPGA development boards for PCI...

Comparison of Zynq boards

If you're interested in testing out the Zynq-7000 SoC from Xilinx there are now quite a few options available, so it comes down to a question of features vs price. Below I've listed the most important features of the available boards side-by-side to help you make the...

Using the AXI DMA Engine

Update 2014-08-06: This tutorial is now available in a Vivado version - Using the AXI DMA in Vivado One of the essential devices for maximizing performance in FPGA designs is the DMA Engine. DMA stands for Direct Memory Access and a DMA engine allows you to transfer...

How to download and build my Github FPGA projects

A while back I started sharing FPGA projects and code on Github. As I typically only commit sources and not generated files, the process of rebuilding the projects from sources can be a little tricky if you're not used to working with the Xilinx tools. In this post...

Create an application using the Xilinx SDK

In the previous tutorial titled Creating a project using Base System Builder, we used Xilinx Platform Studio (EDK) to create a hardware design (bitstream) for the Zynq SoC. In this tutorial, we will complete the design by writing a software application to run on the...

Creating a project using the Base System Builder

I know I've gone through the Base System Builder many times before but I'm writing a few more advanced tutorials for version 14.7 and they all need a starting point. So in this post we will use the handy Base System Builder of the Xilinx Platform Studio (EDK) to put...

JTAG problems with the ZC706

I ran into a problem on the JTAG boundary scan and after hours of googling and probing with my oscilloscope, I finally came across a solution. Firstly I should say that if you are having a JTAG problem with this board, make sure that your DIP switch settings are...

Zynq-7000 ZC706 Evaluation Board

I just received the Zynq-7000 based ZC706 development board from a new client and I'm pretty excited to start working on it. This is the first time that I'll be working on the Zynq FPGA, part of the latest series 7 devices from Xilinx, so over the next few days, I'll...