List of PYNQ projects and ports

List of PYNQ projects and ports
PYNQ enables huge productivity gains by making it possible to program the Zynq-7000 SoC with a high-level programming language (Python) and leverage the power of FPGA hardware acceleration with ease. Xilinx first designed PYNQ to target the PYNQ-Z1 board but it wasn’t long before others saw the potential of running PYNQ on other platforms. This post is a list of open-sourced PYNQ projects and ports that run on other platforms. I’ll keep the list up-to-date but if you know of an open-sourced PYNQ project or port that I haven’t found yet, please let me know and I’ll add it to the list. [Read More]
pynq 

PYNQ Computer Vision demo: 2D filter and dilate

See what the PYNQ-Z1 and the PYNQ Computer Vision overlay are capable of doing with a 720p standard HD video stream. In the video we run a 2D filter and dilate function on the incoming video, first using the Python OpenCV functions (ie. without hardware acceleration), then we test it again with the accelerator IPs running on the FPGA. Without acceleration, we get a frame rate of 5 frames per second. [Read More]
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How to accelerate a Python function with PYNQ

This video demonstrates how you would typically go about accelerating a Python function or algorithm on the Zynq-7000 with PYNQ. The function I chose to base this video on is the Finite Impulse Response (FIR) filter because the SciPy package contains the lfilter function which can be used for this purpose, and because the Xilinx IP catalog has a free FIR filter IP core. If you instead wanted to implement the accelerator in HLS, the process would be very similar, you would just have to design your accelerator with AXI-Streaming interfaces and ensure that the TLAST signals were properly managed. [Read More]

Avnet Silica's industrial networking demo features Ethernet FMC

Avnet Silica was at Embedded World 2018 in Nuremburg, Germany last February demonstrating some cool industrial networking solutions such as TSN and FOSS GNU/Linux security concepts on Opsero’s Robust Ethernet FMC and the Zynq UltraScale+. Get a glimpse of the hardware at 0:54. If you saw the demo in person, I’d love to know what you thought of it.

Create a custom PYNQ overlay for PYNQ-Z1

In this video tutorial we create a custom PYNQ overlay for the PYNQ-Z1 board. Probably the simplest PYNQ overlay possible, it contains one custom IP (an adder) with an AXI-Lite interface and three registers accessible over that interface: a, b and c. To use the IP we write a number to input registers a and b, and then we read the output register c which contains the sum of a and b. [Read More]

Python for the Zynq and the PYNQ-Z1

Being a big fan of Python, for ages I’ve wanted to explore the possibilities of running Python on the Zynq. Thankfully Xilinx and Digilent saw the value in this too and they developed the PYNQ-Z1 and more importantly the PYNQ libraries for Python. The PYNQ-Z1 is basically a single board computer based on the Zynq-7020 device from Xilinx. So thats got a dual core ARM plus integrated FPGA or programmable logic. [Read More]
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IntelliProp Demos NVMe Host Accelerator on FPGA Drive

Early this year IntelliProp released a demo video of their NVMe Host Accelerator IP core running on the Intel Arria 10 GX FPGA Development board. As you can see in the video, they are using Opsero’s FPGA Drive product with the PCIe slot connector to interface the NVMe SSD to the FPGA board. They measured an impressive performance of around 2300MBps sequential write speed and 3200MBps sequential read speed. [Read More]
nvme 

PetaLinux for Artix-7 Arty Base Project

In the final part of the Arty base project tutorial, we build a PetaLinux project that’s tailored to our Arty base design. Then we boot PetaLinux on our hardware and verify that we have network connectivity by checking the Arty’s DHCP assigned IP address and then pinging it from a PC. Tools used I used the following setup to do this project: Vivado 2017.3 on a Windows 10 machine PetaLinux 2017. [Read More]

Artix-7 Arty Base Project

Here’s a base project for the Arty board based on the Artix-7 FPGA. The Arty is a nice little dev board because it’s low cost ($99 USD) but it’s still got enough power and connectivity to make it very useful. I really like the fact that the JTAG and UART are both accessed through the same USB connector, so I only need to connect one USB cable. [Read More]

Creating a custom AXI-Streaming IP in Vivado

The AXI-Streaming interface is important for designs that need to process a stream of data, such as samples coming from an ADC, or images coming from a camera. In this tutorial, we go through the steps to create a custom IP in Vivado with both a slave and master AXI-Streaming interface. The custom IP will be written in Verilog and it will simply buffer the incoming data at the slave interface and make it available at the master interface - in other words, it will be a FIFO. [Read More]